2 * Copyright (c) 2010 The WebM project authors. All Rights Reserved.
4 * Use of this source code is governed by a BSD-style license
5 * that can be found in the LICENSE file in the root of the source
6 * tree. An additional intellectual property rights grant can be found
7 * in the file PATENTS. All contributing project authors may
8 * be found in the AUTHORS file in the root of the source tree.
12 #ifndef VPX_PORTS_X86_H_
13 #define VPX_PORTS_X86_H_
17 #include <intrin.h> /* For __cpuidex, __rdtsc */
20 #include "vpx_config.h"
21 #include "vpx/vpx_integer.h"
39 VPX_CPU_TRANSMETA_OLD,
46 #if defined(__GNUC__) && __GNUC__ || defined(__ANDROID__)
48 #define cpuid(func, func2, ax, bx, cx, dx)\
49 __asm__ __volatile__ (\
51 : "=a" (ax), "=b" (bx), "=c" (cx), "=d" (dx) \
52 : "a" (func), "c" (func2));
54 #define cpuid(func, func2, ax, bx, cx, dx)\
55 __asm__ __volatile__ (\
56 "mov %%ebx, %%edi \n\t" \
58 "xchg %%edi, %%ebx \n\t" \
59 : "=a" (ax), "=D" (bx), "=c" (cx), "=d" (dx) \
60 : "a" (func), "c" (func2));
62 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC) /* end __GNUC__ or __ANDROID__*/
64 #define cpuid(func, func2, ax, bx, cx, dx)\
66 "xchg %rsi, %rbx \n\t" \
68 "movl %ebx, %edi \n\t" \
69 "xchg %rsi, %rbx \n\t" \
70 : "=a" (ax), "=D" (bx), "=c" (cx), "=d" (dx) \
71 : "a" (func), "c" (func2));
73 #define cpuid(func, func2, ax, bx, cx, dx)\
77 "movl %ebx, %edi \n\t" \
79 : "=a" (ax), "=D" (bx), "=c" (cx), "=d" (dx) \
80 : "a" (func), "c" (func2));
82 #else /* end __SUNPRO__ */
84 #if defined(_MSC_VER) && _MSC_VER > 1500
85 #define cpuid(func, func2, a, b, c, d) do {\
87 __cpuidex(regs, func, func2); \
88 a = regs[0]; b = regs[1]; c = regs[2]; d = regs[3];\
91 #define cpuid(func, func2, a, b, c, d) do {\
93 __cpuid(regs, func); \
94 a = regs[0]; b = regs[1]; c = regs[2]; d = regs[3];\
98 #define cpuid(func, func2, a, b, c, d)\
100 __asm mov ecx, func2\
107 #endif /* end others */
109 // NaCl has no support for xgetbv or the raw opcode.
110 #if !defined(__native_client__) && (defined(__i386__) || defined(__x86_64__))
111 static INLINE uint64_t xgetbv(void) {
112 const uint32_t ecx = 0;
114 // Use the raw opcode for xgetbv for compatibility with older toolchains.
116 ".byte 0x0f, 0x01, 0xd0\n"
117 : "=a"(eax), "=d"(edx) : "c" (ecx));
118 return ((uint64_t)edx << 32) | eax;
120 #elif (defined(_M_X64) || defined(_M_IX86)) && \
121 defined(_MSC_FULL_VER) && _MSC_FULL_VER >= 160040219 // >= VS2010 SP1
122 #include <immintrin.h>
123 #define xgetbv() _xgetbv(0)
124 #elif defined(_MSC_VER) && defined(_M_IX86)
125 static INLINE uint64_t xgetbv(void) {
128 xor ecx, ecx // ecx = 0
129 // Use the raw opcode for xgetbv for compatibility with older toolchains.
130 __asm _emit 0x0f __asm _emit 0x01 __asm _emit 0xd0
134 return ((uint64_t)edx_ << 32) | eax_;
137 #define xgetbv() 0U // no AVX for older x64 or unrecognized toolchains.
140 #if defined(_MSC_VER) && _MSC_VER >= 1700
142 #if WINAPI_FAMILY_PARTITION(WINAPI_FAMILY_APP)
143 #define getenv(x) NULL
149 #define HAS_SSE2 0x04
150 #define HAS_SSE3 0x08
151 #define HAS_SSSE3 0x10
152 #define HAS_SSE4_1 0x20
154 #define HAS_AVX2 0x80
156 #define BIT(n) (1<<n)
160 x86_simd_caps(void) {
161 unsigned int flags = 0;
162 unsigned int mask = ~0;
163 unsigned int max_cpuid_val, reg_eax, reg_ebx, reg_ecx, reg_edx;
167 /* See if the CPU capabilities are being overridden by the environment */
168 env = getenv("VPX_SIMD_CAPS");
171 return (int)strtol(env, NULL, 0);
173 env = getenv("VPX_SIMD_CAPS_MASK");
176 mask = (unsigned int)strtoul(env, NULL, 0);
178 /* Ensure that the CPUID instruction supports extended features */
179 cpuid(0, 0, max_cpuid_val, reg_ebx, reg_ecx, reg_edx);
181 if (max_cpuid_val < 1)
184 /* Get the standard feature flags */
185 cpuid(1, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
187 if (reg_edx & BIT(23)) flags |= HAS_MMX;
189 if (reg_edx & BIT(25)) flags |= HAS_SSE; /* aka xmm */
191 if (reg_edx & BIT(26)) flags |= HAS_SSE2; /* aka wmt */
193 if (reg_ecx & BIT(0)) flags |= HAS_SSE3;
195 if (reg_ecx & BIT(9)) flags |= HAS_SSSE3;
197 if (reg_ecx & BIT(19)) flags |= HAS_SSE4_1;
199 // bits 27 (OSXSAVE) & 28 (256-bit AVX)
200 if ((reg_ecx & (BIT(27) | BIT(28))) == (BIT(27) | BIT(28))) {
201 if ((xgetbv() & 0x6) == 0x6) {
204 if (max_cpuid_val >= 7) {
205 /* Get the leaf 7 feature flags. Needed to check for AVX2 support */
206 cpuid(7, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
208 if (reg_ebx & BIT(5)) flags |= HAS_AVX2;
217 // 32-bit CPU cycle counter is light-weighted for most function performance
218 // measurement. For large function (CPU time > a couple of seconds), 64-bit
219 // counter should be used.
220 // 32-bit CPU cycle counter
221 static INLINE unsigned int
223 #if defined(__GNUC__) && __GNUC__
225 __asm__ __volatile__("rdtsc\n\t":"=a"(tsc):);
227 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
229 asm volatile("rdtsc\n\t":"=a"(tsc):);
233 return (unsigned int)__rdtsc();
239 // 64-bit CPU cycle counter
240 static INLINE uint64_t
241 x86_readtsc64(void) {
242 #if defined(__GNUC__) && __GNUC__
244 __asm__ __volatile__("rdtsc" : "=a"(lo), "=d"(hi));
245 return ((uint64_t)hi << 32) | lo;
246 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
248 asm volatile("rdtsc\n\t" : "=a"(lo), "=d"(hi));
249 return ((uint64_t)hi << 32) | lo;
252 return (uint64_t)__rdtsc();
259 #if defined(__GNUC__) && __GNUC__
260 #define x86_pause_hint()\
261 __asm__ __volatile__ ("pause \n\t")
262 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
263 #define x86_pause_hint()\
264 asm volatile ("pause \n\t")
267 #define x86_pause_hint()\
270 #define x86_pause_hint()\
275 #if defined(__GNUC__) && __GNUC__
277 x87_set_control_word(unsigned short mode) {
278 __asm__ __volatile__("fldcw %0" : : "m"(*&mode));
280 static unsigned short
281 x87_get_control_word(void) {
283 __asm__ __volatile__("fstcw %0\n\t":"=m"(*&mode):);
286 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
288 x87_set_control_word(unsigned short mode) {
289 asm volatile("fldcw %0" : : "m"(*&mode));
291 static unsigned short
292 x87_get_control_word(void) {
294 asm volatile("fstcw %0\n\t":"=m"(*&mode):);
298 /* No fldcw intrinsics on Windows x64, punt to external asm */
299 extern void vpx_winx64_fldcw(unsigned short mode);
300 extern unsigned short vpx_winx64_fstcw(void);
301 #define x87_set_control_word vpx_winx64_fldcw
302 #define x87_get_control_word vpx_winx64_fstcw
305 x87_set_control_word(unsigned short mode) {
308 static unsigned short
309 x87_get_control_word(void) {
316 static INLINE unsigned int
317 x87_set_double_precision(void) {
318 unsigned int mode = x87_get_control_word();
319 x87_set_control_word((mode&~0x300) | 0x200);
324 extern void vpx_reset_mmx_state(void);
330 #endif // VPX_PORTS_X86_H_