2 * Copyright (c) 2010 The WebM project authors. All Rights Reserved.
4 * Use of this source code is governed by a BSD-style license
5 * that can be found in the LICENSE file in the root of the source
6 * tree. An additional intellectual property rights grant can be found
7 * in the file PATENTS. All contributing project authors may
8 * be found in the AUTHORS file in the root of the source tree.
11 #ifndef VPX_VPX_PORTS_X86_H_
12 #define VPX_VPX_PORTS_X86_H_
16 #include <intrin.h> /* For __cpuidex, __rdtsc */
19 #include "vpx_config.h"
20 #include "vpx/vpx_integer.h"
38 VPX_CPU_TRANSMETA_OLD,
45 #if defined(__GNUC__) && __GNUC__ || defined(__ANDROID__)
47 #define cpuid(func, func2, ax, bx, cx, dx) \
48 __asm__ __volatile__("cpuid \n\t" \
49 : "=a"(ax), "=b"(bx), "=c"(cx), "=d"(dx) \
50 : "a"(func), "c"(func2));
52 #define cpuid(func, func2, ax, bx, cx, dx) \
53 __asm__ __volatile__( \
54 "mov %%ebx, %%edi \n\t" \
56 "xchg %%edi, %%ebx \n\t" \
57 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
58 : "a"(func), "c"(func2));
60 #elif defined(__SUNPRO_C) || \
61 defined(__SUNPRO_CC) /* end __GNUC__ or __ANDROID__*/
63 #define cpuid(func, func2, ax, bx, cx, dx) \
65 "xchg %rsi, %rbx \n\t" \
67 "movl %ebx, %edi \n\t" \
68 "xchg %rsi, %rbx \n\t" \
69 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
70 : "a"(func), "c"(func2));
72 #define cpuid(func, func2, ax, bx, cx, dx) \
76 "movl %ebx, %edi \n\t" \
78 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
79 : "a"(func), "c"(func2));
81 #else /* end __SUNPRO__ */
83 #if defined(_MSC_VER) && _MSC_VER > 1500
84 #define cpuid(func, func2, a, b, c, d) \
87 __cpuidex(regs, func, func2); \
94 #define cpuid(func, func2, a, b, c, d) \
97 __cpuid(regs, func); \
105 #define cpuid(func, func2, a, b, c, d) \
106 __asm mov eax, func __asm mov ecx, func2 __asm cpuid __asm mov a, \
107 eax __asm mov b, ebx __asm mov c, ecx __asm mov d, edx
109 #endif /* end others */
111 // NaCl has no support for xgetbv or the raw opcode.
112 #if !defined(__native_client__) && (defined(__i386__) || defined(__x86_64__))
113 static INLINE uint64_t xgetbv(void) {
114 const uint32_t ecx = 0;
116 // Use the raw opcode for xgetbv for compatibility with older toolchains.
117 __asm__ volatile(".byte 0x0f, 0x01, 0xd0\n"
118 : "=a"(eax), "=d"(edx)
120 return ((uint64_t)edx << 32) | eax;
122 #elif (defined(_M_X64) || defined(_M_IX86)) && defined(_MSC_FULL_VER) && \
123 _MSC_FULL_VER >= 160040219 // >= VS2010 SP1
124 #include <immintrin.h>
125 #define xgetbv() _xgetbv(0)
126 #elif defined(_MSC_VER) && defined(_M_IX86)
127 static INLINE uint64_t xgetbv(void) {
130 xor ecx, ecx // ecx = 0
131 // Use the raw opcode for xgetbv for compatibility with older toolchains.
132 __asm _emit 0x0f __asm _emit 0x01 __asm _emit 0xd0
136 return ((uint64_t)edx_ << 32) | eax_;
139 #define xgetbv() 0U // no AVX for older x64 or unrecognized toolchains.
142 #if defined(_MSC_VER) && _MSC_VER >= 1700
145 #ifndef WIN32_LEAN_AND_MEAN
146 #define WIN32_LEAN_AND_MEAN
149 #if WINAPI_FAMILY_PARTITION(WINAPI_FAMILY_APP)
150 #define getenv(x) NULL
154 #define HAS_MMX 0x001
155 #define HAS_SSE 0x002
156 #define HAS_SSE2 0x004
157 #define HAS_SSE3 0x008
158 #define HAS_SSSE3 0x010
159 #define HAS_SSE4_1 0x020
160 #define HAS_AVX 0x040
161 #define HAS_AVX2 0x080
162 #define HAS_AVX512 0x100
164 #define BIT(n) (1u << n)
167 static INLINE int x86_simd_caps(void) {
168 unsigned int flags = 0;
169 unsigned int mask = ~0;
170 unsigned int max_cpuid_val, reg_eax, reg_ebx, reg_ecx, reg_edx;
174 /* See if the CPU capabilities are being overridden by the environment */
175 env = getenv("VPX_SIMD_CAPS");
177 if (env && *env) return (int)strtol(env, NULL, 0);
179 env = getenv("VPX_SIMD_CAPS_MASK");
181 if (env && *env) mask = (unsigned int)strtoul(env, NULL, 0);
183 /* Ensure that the CPUID instruction supports extended features */
184 cpuid(0, 0, max_cpuid_val, reg_ebx, reg_ecx, reg_edx);
186 if (max_cpuid_val < 1) return 0;
188 /* Get the standard feature flags */
189 cpuid(1, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
191 if (reg_edx & BIT(23)) flags |= HAS_MMX;
193 if (reg_edx & BIT(25)) flags |= HAS_SSE; /* aka xmm */
195 if (reg_edx & BIT(26)) flags |= HAS_SSE2; /* aka wmt */
197 if (reg_ecx & BIT(0)) flags |= HAS_SSE3;
199 if (reg_ecx & BIT(9)) flags |= HAS_SSSE3;
201 if (reg_ecx & BIT(19)) flags |= HAS_SSE4_1;
203 // bits 27 (OSXSAVE) & 28 (256-bit AVX)
204 if ((reg_ecx & (BIT(27) | BIT(28))) == (BIT(27) | BIT(28))) {
205 if ((xgetbv() & 0x6) == 0x6) {
208 if (max_cpuid_val >= 7) {
209 /* Get the leaf 7 feature flags. Needed to check for AVX2 support */
210 cpuid(7, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
212 if (reg_ebx & BIT(5)) flags |= HAS_AVX2;
214 // bits 16 (AVX-512F) & 17 (AVX-512DQ) & 28 (AVX-512CD) &
215 // 30 (AVX-512BW) & 32 (AVX-512VL)
216 if ((reg_ebx & (BIT(16) | BIT(17) | BIT(28) | BIT(30) | BIT(31))) ==
217 (BIT(16) | BIT(17) | BIT(28) | BIT(30) | BIT(31)))
226 // Fine-Grain Measurement Functions
228 // If you are timing a small region of code, access the timestamp counter
231 // unsigned int start = x86_tsc_start();
233 // unsigned int end = x86_tsc_end();
234 // unsigned int diff = end - start;
236 // The start/end functions introduce a few more instructions than using
237 // x86_readtsc directly, but prevent the CPU's out-of-order execution from
238 // affecting the measurement (by having earlier/later instructions be evaluated
239 // in the time interval). See the white paper, "How to Benchmark Code
240 // Execution Times on IntelĀ® IA-32 and IA-64 Instruction Set Architectures" by
241 // Gabriele Paoloni for more information.
243 // If you are timing a large function (CPU time > a couple of seconds), use
244 // x86_readtsc64 to read the timestamp counter in a 64-bit integer. The
245 // out-of-order leakage that can occur is minimal compared to total runtime.
246 static INLINE unsigned int x86_readtsc(void) {
247 #if defined(__GNUC__) && __GNUC__
249 __asm__ __volatile__("rdtsc\n\t" : "=a"(tsc) :);
251 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
253 asm volatile("rdtsc\n\t" : "=a"(tsc) :);
257 return (unsigned int)__rdtsc();
263 // 64-bit CPU cycle counter
264 static INLINE uint64_t x86_readtsc64(void) {
265 #if defined(__GNUC__) && __GNUC__
267 __asm__ __volatile__("rdtsc" : "=a"(lo), "=d"(hi));
268 return ((uint64_t)hi << 32) | lo;
269 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
271 asm volatile("rdtsc\n\t" : "=a"(lo), "=d"(hi));
272 return ((uint64_t)hi << 32) | lo;
275 return (uint64_t)__rdtsc();
282 // 32-bit CPU cycle counter with a partial fence against out-of-order execution.
283 static INLINE unsigned int x86_readtscp(void) {
284 #if defined(__GNUC__) && __GNUC__
286 __asm__ __volatile__("rdtscp\n\t" : "=a"(tscp) :);
288 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
290 asm volatile("rdtscp\n\t" : "=a"(tscp) :);
292 #elif defined(_MSC_VER)
294 return (unsigned int)__rdtscp(&ui);
297 return (unsigned int)__rdtscp();
304 static INLINE unsigned int x86_tsc_start(void) {
305 unsigned int reg_eax, reg_ebx, reg_ecx, reg_edx;
306 cpuid(0, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
307 return x86_readtsc();
310 static INLINE unsigned int x86_tsc_end(void) {
311 uint32_t v = x86_readtscp();
312 unsigned int reg_eax, reg_ebx, reg_ecx, reg_edx;
313 cpuid(0, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
317 #if defined(__GNUC__) && __GNUC__
318 #define x86_pause_hint() __asm__ __volatile__("pause \n\t")
319 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
320 #define x86_pause_hint() asm volatile("pause \n\t")
323 #define x86_pause_hint() _mm_pause();
325 #define x86_pause_hint() __asm pause
329 #if defined(__GNUC__) && __GNUC__
330 static void x87_set_control_word(unsigned short mode) {
331 __asm__ __volatile__("fldcw %0" : : "m"(*&mode));
333 static unsigned short x87_get_control_word(void) {
335 __asm__ __volatile__("fstcw %0\n\t" : "=m"(*&mode) :);
338 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
339 static void x87_set_control_word(unsigned short mode) {
340 asm volatile("fldcw %0" : : "m"(*&mode));
342 static unsigned short x87_get_control_word(void) {
344 asm volatile("fstcw %0\n\t" : "=m"(*&mode) :);
348 /* No fldcw intrinsics on Windows x64, punt to external asm */
349 extern void vpx_winx64_fldcw(unsigned short mode);
350 extern unsigned short vpx_winx64_fstcw(void);
351 #define x87_set_control_word vpx_winx64_fldcw
352 #define x87_get_control_word vpx_winx64_fstcw
354 static void x87_set_control_word(unsigned short mode) {
357 static unsigned short x87_get_control_word(void) {
364 static INLINE unsigned int x87_set_double_precision(void) {
365 unsigned int mode = x87_get_control_word();
366 // Intel 64 and IA-32 Architectures Developer's Manual: Vol. 1
367 // https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf
368 // 8.1.5.2 Precision Control Field
369 // Bits 8 and 9 (0x300) of the x87 FPU Control Word ("Precision Control")
370 // determine the number of bits used in floating point calculations. To match
371 // later SSE instructions restrict x87 operations to Double Precision (0x200).
372 // Precision PC Field
373 // Single Precision (24-Bits) 00B
375 // Double Precision (53-Bits) 10B
376 // Extended Precision (64-Bits) 11B
377 x87_set_control_word((mode & ~0x300) | 0x200);
385 #endif // VPX_VPX_PORTS_X86_H_