2 * Copyright (c) 2010 The WebM project authors. All Rights Reserved.
4 * Use of this source code is governed by a BSD-style license
5 * that can be found in the LICENSE file in the root of the source
6 * tree. An additional intellectual property rights grant can be found
7 * in the file PATENTS. All contributing project authors may
8 * be found in the AUTHORS file in the root of the source tree.
11 #ifndef VPX_PORTS_X86_H_
12 #define VPX_PORTS_X86_H_
16 #include <intrin.h> /* For __cpuidex, __rdtsc */
19 #include "vpx_config.h"
20 #include "vpx/vpx_integer.h"
38 VPX_CPU_TRANSMETA_OLD,
45 #if defined(__GNUC__) && __GNUC__ || defined(__ANDROID__)
47 #define cpuid(func, func2, ax, bx, cx, dx) \
48 __asm__ __volatile__("cpuid \n\t" \
49 : "=a"(ax), "=b"(bx), "=c"(cx), "=d"(dx) \
50 : "a"(func), "c"(func2));
52 #define cpuid(func, func2, ax, bx, cx, dx) \
53 __asm__ __volatile__( \
54 "mov %%ebx, %%edi \n\t" \
56 "xchg %%edi, %%ebx \n\t" \
57 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
58 : "a"(func), "c"(func2));
60 #elif defined(__SUNPRO_C) || \
61 defined(__SUNPRO_CC) /* end __GNUC__ or __ANDROID__*/
63 #define cpuid(func, func2, ax, bx, cx, dx) \
65 "xchg %rsi, %rbx \n\t" \
67 "movl %ebx, %edi \n\t" \
68 "xchg %rsi, %rbx \n\t" \
69 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
70 : "a"(func), "c"(func2));
72 #define cpuid(func, func2, ax, bx, cx, dx) \
76 "movl %ebx, %edi \n\t" \
78 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
79 : "a"(func), "c"(func2));
81 #else /* end __SUNPRO__ */
83 #if defined(_MSC_VER) && _MSC_VER > 1500
84 #define cpuid(func, func2, a, b, c, d) \
87 __cpuidex(regs, func, func2); \
94 #define cpuid(func, func2, a, b, c, d) \
97 __cpuid(regs, func); \
105 #define cpuid(func, func2, a, b, c, d) \
106 __asm mov eax, func __asm mov ecx, func2 __asm cpuid __asm mov a, \
107 eax __asm mov b, ebx __asm mov c, ecx __asm mov d, edx
109 #endif /* end others */
111 // NaCl has no support for xgetbv or the raw opcode.
112 #if !defined(__native_client__) && (defined(__i386__) || defined(__x86_64__))
113 static INLINE uint64_t xgetbv(void) {
114 const uint32_t ecx = 0;
116 // Use the raw opcode for xgetbv for compatibility with older toolchains.
117 __asm__ volatile(".byte 0x0f, 0x01, 0xd0\n"
118 : "=a"(eax), "=d"(edx)
120 return ((uint64_t)edx << 32) | eax;
122 #elif (defined(_M_X64) || defined(_M_IX86)) && defined(_MSC_FULL_VER) && \
123 _MSC_FULL_VER >= 160040219 // >= VS2010 SP1
124 #include <immintrin.h>
125 #define xgetbv() _xgetbv(0)
126 #elif defined(_MSC_VER) && defined(_M_IX86)
127 static INLINE uint64_t xgetbv(void) {
130 xor ecx, ecx // ecx = 0
131 // Use the raw opcode for xgetbv for compatibility with older toolchains.
132 __asm _emit 0x0f __asm _emit 0x01 __asm _emit 0xd0
136 return ((uint64_t)edx_ << 32) | eax_;
139 #define xgetbv() 0U // no AVX for older x64 or unrecognized toolchains.
142 #if defined(_MSC_VER) && _MSC_VER >= 1700
145 #ifndef WIN32_LEAN_AND_MEAN
146 #define WIN32_LEAN_AND_MEAN
149 #if WINAPI_FAMILY_PARTITION(WINAPI_FAMILY_APP)
150 #define getenv(x) NULL
156 #define HAS_SSE2 0x04
157 #define HAS_SSE3 0x08
158 #define HAS_SSSE3 0x10
159 #define HAS_SSE4_1 0x20
161 #define HAS_AVX2 0x80
163 #define BIT(n) (1 << n)
166 static INLINE int x86_simd_caps(void) {
167 unsigned int flags = 0;
168 unsigned int mask = ~0;
169 unsigned int max_cpuid_val, reg_eax, reg_ebx, reg_ecx, reg_edx;
173 /* See if the CPU capabilities are being overridden by the environment */
174 env = getenv("VPX_SIMD_CAPS");
176 if (env && *env) return (int)strtol(env, NULL, 0);
178 env = getenv("VPX_SIMD_CAPS_MASK");
180 if (env && *env) mask = (unsigned int)strtoul(env, NULL, 0);
182 /* Ensure that the CPUID instruction supports extended features */
183 cpuid(0, 0, max_cpuid_val, reg_ebx, reg_ecx, reg_edx);
185 if (max_cpuid_val < 1) return 0;
187 /* Get the standard feature flags */
188 cpuid(1, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
190 if (reg_edx & BIT(23)) flags |= HAS_MMX;
192 if (reg_edx & BIT(25)) flags |= HAS_SSE; /* aka xmm */
194 if (reg_edx & BIT(26)) flags |= HAS_SSE2; /* aka wmt */
196 if (reg_ecx & BIT(0)) flags |= HAS_SSE3;
198 if (reg_ecx & BIT(9)) flags |= HAS_SSSE3;
200 if (reg_ecx & BIT(19)) flags |= HAS_SSE4_1;
202 // bits 27 (OSXSAVE) & 28 (256-bit AVX)
203 if ((reg_ecx & (BIT(27) | BIT(28))) == (BIT(27) | BIT(28))) {
204 if ((xgetbv() & 0x6) == 0x6) {
207 if (max_cpuid_val >= 7) {
208 /* Get the leaf 7 feature flags. Needed to check for AVX2 support */
209 cpuid(7, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
211 if (reg_ebx & BIT(5)) flags |= HAS_AVX2;
220 // 32-bit CPU cycle counter is light-weighted for most function performance
221 // measurement. For large function (CPU time > a couple of seconds), 64-bit
222 // counter should be used.
223 // 32-bit CPU cycle counter
224 static INLINE unsigned int x86_readtsc(void) {
225 #if defined(__GNUC__) && __GNUC__
227 __asm__ __volatile__("rdtsc\n\t" : "=a"(tsc) :);
229 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
231 asm volatile("rdtsc\n\t" : "=a"(tsc) :);
235 return (unsigned int)__rdtsc();
241 // 64-bit CPU cycle counter
242 static INLINE uint64_t x86_readtsc64(void) {
243 #if defined(__GNUC__) && __GNUC__
245 __asm__ __volatile__("rdtsc" : "=a"(lo), "=d"(hi));
246 return ((uint64_t)hi << 32) | lo;
247 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
249 asm volatile("rdtsc\n\t" : "=a"(lo), "=d"(hi));
250 return ((uint64_t)hi << 32) | lo;
253 return (uint64_t)__rdtsc();
260 #if defined(__GNUC__) && __GNUC__
261 #define x86_pause_hint() __asm__ __volatile__("pause \n\t")
262 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
263 #define x86_pause_hint() asm volatile("pause \n\t")
266 #define x86_pause_hint() _mm_pause();
268 #define x86_pause_hint() __asm pause
272 #if defined(__GNUC__) && __GNUC__
273 static void x87_set_control_word(unsigned short mode) {
274 __asm__ __volatile__("fldcw %0" : : "m"(*&mode));
276 static unsigned short x87_get_control_word(void) {
278 __asm__ __volatile__("fstcw %0\n\t" : "=m"(*&mode) :);
281 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
282 static void x87_set_control_word(unsigned short mode) {
283 asm volatile("fldcw %0" : : "m"(*&mode));
285 static unsigned short x87_get_control_word(void) {
287 asm volatile("fstcw %0\n\t" : "=m"(*&mode) :);
291 /* No fldcw intrinsics on Windows x64, punt to external asm */
292 extern void vpx_winx64_fldcw(unsigned short mode);
293 extern unsigned short vpx_winx64_fstcw(void);
294 #define x87_set_control_word vpx_winx64_fldcw
295 #define x87_get_control_word vpx_winx64_fstcw
297 static void x87_set_control_word(unsigned short mode) {
300 static unsigned short x87_get_control_word(void) {
307 static INLINE unsigned int x87_set_double_precision(void) {
308 unsigned int mode = x87_get_control_word();
309 x87_set_control_word((mode & ~0x300) | 0x200);
313 extern void vpx_reset_mmx_state(void);
319 #endif // VPX_PORTS_X86_H_