granicus.if.org Git - strace/blob - process.c

   1 /*
   2  * Copyright (c) 1991, 1992 Paul Kranenburg <pk@cs.few.eur.nl>
   3  * Copyright (c) 1993 Branko Lankester <branko@hacktic.nl>
   4  * Copyright (c) 1993, 1994, 1995, 1996 Rick Sladkey <jrs@world.std.com>
   5  * Copyright (c) 1996-1999 Wichert Akkerman <wichert@cistron.nl>
   6  * Copyright (c) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
   7  *                     Linux for s390 port by D.J. Barrow
   8  *                    <barrow_dj@mail.yahoo.com,djbarrow@de.ibm.com>
   9  * Copyright (c) 2000 PocketPenguins Inc.  Linux for Hitachi SuperH
  10  *                    port by Greg Banks <gbanks@pocketpenguins.com>
  11  *
  12  * All rights reserved.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions
  16  * are met:
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in the
  21  *    documentation and/or other materials provided with the distribution.
  22  * 3. The name of the author may not be used to endorse or promote products
  23  *    derived from this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  26  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  27  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  28  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  29  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  30  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  34  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #include "defs.h"
  38 #include <fcntl.h>
  39 #include <sys/stat.h>
  40 #include <sys/user.h>
  41 #ifdef HAVE_ELF_H
  42 # include <elf.h>
  43 #endif
  44
  45 #ifdef HAVE_SYS_REG_H
  46 # include <sys/reg.h>
  47 #endif
  48
  49 #ifdef HAVE_LINUX_PTRACE_H
  50 # undef PTRACE_SYSCALL
  51 # ifdef HAVE_STRUCT_IA64_FPREG
  52 #  define ia64_fpreg XXX_ia64_fpreg
  53 # endif
  54 # ifdef HAVE_STRUCT_PT_ALL_USER_REGS
  55 #  define pt_all_user_regs XXX_pt_all_user_regs
  56 # endif
  57 # ifdef HAVE_STRUCT_PTRACE_PEEKSIGINFO_ARGS
  58 #  define ptrace_peeksiginfo_args XXX_ptrace_peeksiginfo_args
  59 # endif
  60 # include <linux/ptrace.h>
  61 # undef ptrace_peeksiginfo_args
  62 # undef ia64_fpreg
  63 # undef pt_all_user_regs
  64 #endif
  65
  66 #if defined(SPARC64)
  67 # define r_pc r_tpc
  68 # undef PTRACE_GETREGS
  69 # define PTRACE_GETREGS PTRACE_GETREGS64
  70 # undef PTRACE_SETREGS
  71 # define PTRACE_SETREGS PTRACE_SETREGS64
  72 #endif
  73
  74 #if defined(IA64)
  75 # include <asm/ptrace_offsets.h>
  76 # include <asm/rse.h>
  77 #endif
  78
  79 int
  80 sys_sethostname(struct tcb *tcp)
  81 {
  82         if (entering(tcp)) {
  83                 printstr(tcp, tcp->u_arg[0], tcp->u_arg[1]);
  84                 tprintf(", %lu", tcp->u_arg[1]);
  85         }
  86         return 0;
  87 }
  88
  89 #if defined(ALPHA)
  90 int
  91 sys_gethostname(struct tcb *tcp)
  92 {
  93         if (exiting(tcp)) {
  94                 if (syserror(tcp))
  95                         tprintf("%#lx", tcp->u_arg[0]);
  96                 else
  97                         printstr(tcp, tcp->u_arg[0], -1);
  98                 tprintf(", %lu", tcp->u_arg[1]);
  99         }
 100         return 0;
 101 }
 102 #endif
 103
 104 int
 105 sys_exit(struct tcb *tcp)
 106 {
 107         if (exiting(tcp)) {
 108                 fprintf(stderr, "_exit returned!\n");
 109                 return -1;
 110         }
 111         /* special case: we stop tracing this process, finish line now */
 112         tprintf("%ld) ", tcp->u_arg[0]);
 113         tabto();
 114         tprints("= ?\n");
 115         line_ended();
 116         return 0;
 117 }
 118
 119 #include "xlat/ptrace_cmds.h"
 120 #include "xlat/ptrace_setoptions_flags.h"
 121 #include "xlat/nt_descriptor_types.h"
 122
 123 #define uoff(member)    offsetof(struct user, member)
 124
 125 const struct xlat struct_user_offsets[] = {
 126 #if defined(S390) || defined(S390X)
 127         { PT_PSWMASK,           "psw_mask"                              },
 128         { PT_PSWADDR,           "psw_addr"                              },
 129         { PT_GPR0,              "gpr0"                                  },
 130         { PT_GPR1,              "gpr1"                                  },
 131         { PT_GPR2,              "gpr2"                                  },
 132         { PT_GPR3,              "gpr3"                                  },
 133         { PT_GPR4,              "gpr4"                                  },
 134         { PT_GPR5,              "gpr5"                                  },
 135         { PT_GPR6,              "gpr6"                                  },
 136         { PT_GPR7,              "gpr7"                                  },
 137         { PT_GPR8,              "gpr8"                                  },
 138         { PT_GPR9,              "gpr9"                                  },
 139         { PT_GPR10,             "gpr10"                                 },
 140         { PT_GPR11,             "gpr11"                                 },
 141         { PT_GPR12,             "gpr12"                                 },
 142         { PT_GPR13,             "gpr13"                                 },
 143         { PT_GPR14,             "gpr14"                                 },
 144         { PT_GPR15,             "gpr15"                                 },
 145         { PT_ACR0,              "acr0"                                  },
 146         { PT_ACR1,              "acr1"                                  },
 147         { PT_ACR2,              "acr2"                                  },
 148         { PT_ACR3,              "acr3"                                  },
 149         { PT_ACR4,              "acr4"                                  },
 150         { PT_ACR5,              "acr5"                                  },
 151         { PT_ACR6,              "acr6"                                  },
 152         { PT_ACR7,              "acr7"                                  },
 153         { PT_ACR8,              "acr8"                                  },
 154         { PT_ACR9,              "acr9"                                  },
 155         { PT_ACR10,             "acr10"                                 },
 156         { PT_ACR11,             "acr11"                                 },
 157         { PT_ACR12,             "acr12"                                 },
 158         { PT_ACR13,             "acr13"                                 },
 159         { PT_ACR14,             "acr14"                                 },
 160         { PT_ACR15,             "acr15"                                 },
 161         { PT_ORIGGPR2,          "orig_gpr2"                             },
 162         { PT_FPC,               "fpc"                                   },
 163 #if defined(S390)
 164         { PT_FPR0_HI,           "fpr0.hi"                               },
 165         { PT_FPR0_LO,           "fpr0.lo"                               },
 166         { PT_FPR1_HI,           "fpr1.hi"                               },
 167         { PT_FPR1_LO,           "fpr1.lo"                               },
 168         { PT_FPR2_HI,           "fpr2.hi"                               },
 169         { PT_FPR2_LO,           "fpr2.lo"                               },
 170         { PT_FPR3_HI,           "fpr3.hi"                               },
 171         { PT_FPR3_LO,           "fpr3.lo"                               },
 172         { PT_FPR4_HI,           "fpr4.hi"                               },
 173         { PT_FPR4_LO,           "fpr4.lo"                               },
 174         { PT_FPR5_HI,           "fpr5.hi"                               },
 175         { PT_FPR5_LO,           "fpr5.lo"                               },
 176         { PT_FPR6_HI,           "fpr6.hi"                               },
 177         { PT_FPR6_LO,           "fpr6.lo"                               },
 178         { PT_FPR7_HI,           "fpr7.hi"                               },
 179         { PT_FPR7_LO,           "fpr7.lo"                               },
 180         { PT_FPR8_HI,           "fpr8.hi"                               },
 181         { PT_FPR8_LO,           "fpr8.lo"                               },
 182         { PT_FPR9_HI,           "fpr9.hi"                               },
 183         { PT_FPR9_LO,           "fpr9.lo"                               },
 184         { PT_FPR10_HI,          "fpr10.hi"                              },
 185         { PT_FPR10_LO,          "fpr10.lo"                              },
 186         { PT_FPR11_HI,          "fpr11.hi"                              },
 187         { PT_FPR11_LO,          "fpr11.lo"                              },
 188         { PT_FPR12_HI,          "fpr12.hi"                              },
 189         { PT_FPR12_LO,          "fpr12.lo"                              },
 190         { PT_FPR13_HI,          "fpr13.hi"                              },
 191         { PT_FPR13_LO,          "fpr13.lo"                              },
 192         { PT_FPR14_HI,          "fpr14.hi"                              },
 193         { PT_FPR14_LO,          "fpr14.lo"                              },
 194         { PT_FPR15_HI,          "fpr15.hi"                              },
 195         { PT_FPR15_LO,          "fpr15.lo"                              },
 196 #endif
 197 #if defined(S390X)
 198         { PT_FPR0,              "fpr0"                                  },
 199         { PT_FPR1,              "fpr1"                                  },
 200         { PT_FPR2,              "fpr2"                                  },
 201         { PT_FPR3,              "fpr3"                                  },
 202         { PT_FPR4,              "fpr4"                                  },
 203         { PT_FPR5,              "fpr5"                                  },
 204         { PT_FPR6,              "fpr6"                                  },
 205         { PT_FPR7,              "fpr7"                                  },
 206         { PT_FPR8,              "fpr8"                                  },
 207         { PT_FPR9,              "fpr9"                                  },
 208         { PT_FPR10,             "fpr10"                                 },
 209         { PT_FPR11,             "fpr11"                                 },
 210         { PT_FPR12,             "fpr12"                                 },
 211         { PT_FPR13,             "fpr13"                                 },
 212         { PT_FPR14,             "fpr14"                                 },
 213         { PT_FPR15,             "fpr15"                                 },
 214 #endif
 215         { PT_CR_9,              "cr9"                                   },
 216         { PT_CR_10,             "cr10"                                  },
 217         { PT_CR_11,             "cr11"                                  },
 218         { PT_IEEE_IP,           "ieee_exception_ip"                     },
 219 #elif defined(SPARC)
 220         /* XXX No support for these offsets yet. */
 221 #elif defined(HPPA)
 222         /* XXX No support for these offsets yet. */
 223 #elif defined(POWERPC)
 224 # ifndef PT_ORIG_R3
 225 #  define PT_ORIG_R3 34
 226 # endif
 227 # define REGSIZE (sizeof(unsigned long))
 228         { REGSIZE*PT_R0,                "r0"                            },
 229         { REGSIZE*PT_R1,                "r1"                            },
 230         { REGSIZE*PT_R2,                "r2"                            },
 231         { REGSIZE*PT_R3,                "r3"                            },
 232         { REGSIZE*PT_R4,                "r4"                            },
 233         { REGSIZE*PT_R5,                "r5"                            },
 234         { REGSIZE*PT_R6,                "r6"                            },
 235         { REGSIZE*PT_R7,                "r7"                            },
 236         { REGSIZE*PT_R8,                "r8"                            },
 237         { REGSIZE*PT_R9,                "r9"                            },
 238         { REGSIZE*PT_R10,               "r10"                           },
 239         { REGSIZE*PT_R11,               "r11"                           },
 240         { REGSIZE*PT_R12,               "r12"                           },
 241         { REGSIZE*PT_R13,               "r13"                           },
 242         { REGSIZE*PT_R14,               "r14"                           },
 243         { REGSIZE*PT_R15,               "r15"                           },
 244         { REGSIZE*PT_R16,               "r16"                           },
 245         { REGSIZE*PT_R17,               "r17"                           },
 246         { REGSIZE*PT_R18,               "r18"                           },
 247         { REGSIZE*PT_R19,               "r19"                           },
 248         { REGSIZE*PT_R20,               "r20"                           },
 249         { REGSIZE*PT_R21,               "r21"                           },
 250         { REGSIZE*PT_R22,               "r22"                           },
 251         { REGSIZE*PT_R23,               "r23"                           },
 252         { REGSIZE*PT_R24,               "r24"                           },
 253         { REGSIZE*PT_R25,               "r25"                           },
 254         { REGSIZE*PT_R26,               "r26"                           },
 255         { REGSIZE*PT_R27,               "r27"                           },
 256         { REGSIZE*PT_R28,               "r28"                           },
 257         { REGSIZE*PT_R29,               "r29"                           },
 258         { REGSIZE*PT_R30,               "r30"                           },
 259         { REGSIZE*PT_R31,               "r31"                           },
 260         { REGSIZE*PT_NIP,               "NIP"                           },
 261         { REGSIZE*PT_MSR,               "MSR"                           },
 262         { REGSIZE*PT_ORIG_R3,           "ORIG_R3"                       },
 263         { REGSIZE*PT_CTR,               "CTR"                           },
 264         { REGSIZE*PT_LNK,               "LNK"                           },
 265         { REGSIZE*PT_XER,               "XER"                           },
 266         { REGSIZE*PT_CCR,               "CCR"                           },
 267         { REGSIZE*PT_FPR0,              "FPR0"                          },
 268 # undef REGSIZE
 269 #elif defined(ALPHA)
 270         { 0,                    "r0"                                    },
 271         { 1,                    "r1"                                    },
 272         { 2,                    "r2"                                    },
 273         { 3,                    "r3"                                    },
 274         { 4,                    "r4"                                    },
 275         { 5,                    "r5"                                    },
 276         { 6,                    "r6"                                    },
 277         { 7,                    "r7"                                    },
 278         { 8,                    "r8"                                    },
 279         { 9,                    "r9"                                    },
 280         { 10,                   "r10"                                   },
 281         { 11,                   "r11"                                   },
 282         { 12,                   "r12"                                   },
 283         { 13,                   "r13"                                   },
 284         { 14,                   "r14"                                   },
 285         { 15,                   "r15"                                   },
 286         { 16,                   "r16"                                   },
 287         { 17,                   "r17"                                   },
 288         { 18,                   "r18"                                   },
 289         { 19,                   "r19"                                   },
 290         { 20,                   "r20"                                   },
 291         { 21,                   "r21"                                   },
 292         { 22,                   "r22"                                   },
 293         { 23,                   "r23"                                   },
 294         { 24,                   "r24"                                   },
 295         { 25,                   "r25"                                   },
 296         { 26,                   "r26"                                   },
 297         { 27,                   "r27"                                   },
 298         { 28,                   "r28"                                   },
 299         { 29,                   "gp"                                    },
 300         { 30,                   "fp"                                    },
 301         { 31,                   "zero"                                  },
 302         { 32,                   "fp0"                                   },
 303         { 33,                   "fp"                                    },
 304         { 34,                   "fp2"                                   },
 305         { 35,                   "fp3"                                   },
 306         { 36,                   "fp4"                                   },
 307         { 37,                   "fp5"                                   },
 308         { 38,                   "fp6"                                   },
 309         { 39,                   "fp7"                                   },
 310         { 40,                   "fp8"                                   },
 311         { 41,                   "fp9"                                   },
 312         { 42,                   "fp10"                                  },
 313         { 43,                   "fp11"                                  },
 314         { 44,                   "fp12"                                  },
 315         { 45,                   "fp13"                                  },
 316         { 46,                   "fp14"                                  },
 317         { 47,                   "fp15"                                  },
 318         { 48,                   "fp16"                                  },
 319         { 49,                   "fp17"                                  },
 320         { 50,                   "fp18"                                  },
 321         { 51,                   "fp19"                                  },
 322         { 52,                   "fp20"                                  },
 323         { 53,                   "fp21"                                  },
 324         { 54,                   "fp22"                                  },
 325         { 55,                   "fp23"                                  },
 326         { 56,                   "fp24"                                  },
 327         { 57,                   "fp25"                                  },
 328         { 58,                   "fp26"                                  },
 329         { 59,                   "fp27"                                  },
 330         { 60,                   "fp28"                                  },
 331         { 61,                   "fp29"                                  },
 332         { 62,                   "fp30"                                  },
 333         { 63,                   "fp31"                                  },
 334         { 64,                   "pc"                                    },
 335 #elif defined(IA64)
 336         { PT_F32, "f32" }, { PT_F33, "f33" }, { PT_F34, "f34" },
 337         { PT_F35, "f35" }, { PT_F36, "f36" }, { PT_F37, "f37" },
 338         { PT_F38, "f38" }, { PT_F39, "f39" }, { PT_F40, "f40" },
 339         { PT_F41, "f41" }, { PT_F42, "f42" }, { PT_F43, "f43" },
 340         { PT_F44, "f44" }, { PT_F45, "f45" }, { PT_F46, "f46" },
 341         { PT_F47, "f47" }, { PT_F48, "f48" }, { PT_F49, "f49" },
 342         { PT_F50, "f50" }, { PT_F51, "f51" }, { PT_F52, "f52" },
 343         { PT_F53, "f53" }, { PT_F54, "f54" }, { PT_F55, "f55" },
 344         { PT_F56, "f56" }, { PT_F57, "f57" }, { PT_F58, "f58" },
 345         { PT_F59, "f59" }, { PT_F60, "f60" }, { PT_F61, "f61" },
 346         { PT_F62, "f62" }, { PT_F63, "f63" }, { PT_F64, "f64" },
 347         { PT_F65, "f65" }, { PT_F66, "f66" }, { PT_F67, "f67" },
 348         { PT_F68, "f68" }, { PT_F69, "f69" }, { PT_F70, "f70" },
 349         { PT_F71, "f71" }, { PT_F72, "f72" }, { PT_F73, "f73" },
 350         { PT_F74, "f74" }, { PT_F75, "f75" }, { PT_F76, "f76" },
 351         { PT_F77, "f77" }, { PT_F78, "f78" }, { PT_F79, "f79" },
 352         { PT_F80, "f80" }, { PT_F81, "f81" }, { PT_F82, "f82" },
 353         { PT_F83, "f83" }, { PT_F84, "f84" }, { PT_F85, "f85" },
 354         { PT_F86, "f86" }, { PT_F87, "f87" }, { PT_F88, "f88" },
 355         { PT_F89, "f89" }, { PT_F90, "f90" }, { PT_F91, "f91" },
 356         { PT_F92, "f92" }, { PT_F93, "f93" }, { PT_F94, "f94" },
 357         { PT_F95, "f95" }, { PT_F96, "f96" }, { PT_F97, "f97" },
 358         { PT_F98, "f98" }, { PT_F99, "f99" }, { PT_F100, "f100" },
 359         { PT_F101, "f101" }, { PT_F102, "f102" }, { PT_F103, "f103" },
 360         { PT_F104, "f104" }, { PT_F105, "f105" }, { PT_F106, "f106" },
 361         { PT_F107, "f107" }, { PT_F108, "f108" }, { PT_F109, "f109" },
 362         { PT_F110, "f110" }, { PT_F111, "f111" }, { PT_F112, "f112" },
 363         { PT_F113, "f113" }, { PT_F114, "f114" }, { PT_F115, "f115" },
 364         { PT_F116, "f116" }, { PT_F117, "f117" }, { PT_F118, "f118" },
 365         { PT_F119, "f119" }, { PT_F120, "f120" }, { PT_F121, "f121" },
 366         { PT_F122, "f122" }, { PT_F123, "f123" }, { PT_F124, "f124" },
 367         { PT_F125, "f125" }, { PT_F126, "f126" }, { PT_F127, "f127" },
 368         /* switch stack: */
 369         { PT_F2, "f2" }, { PT_F3, "f3" }, { PT_F4, "f4" },
 370         { PT_F5, "f5" }, { PT_F10, "f10" }, { PT_F11, "f11" },
 371         { PT_F12, "f12" }, { PT_F13, "f13" }, { PT_F14, "f14" },
 372         { PT_F15, "f15" }, { PT_F16, "f16" }, { PT_F17, "f17" },
 373         { PT_F18, "f18" }, { PT_F19, "f19" }, { PT_F20, "f20" },
 374         { PT_F21, "f21" }, { PT_F22, "f22" }, { PT_F23, "f23" },
 375         { PT_F24, "f24" }, { PT_F25, "f25" }, { PT_F26, "f26" },
 376         { PT_F27, "f27" }, { PT_F28, "f28" }, { PT_F29, "f29" },
 377         { PT_F30, "f30" }, { PT_F31, "f31" }, { PT_R4, "r4" },
 378         { PT_R5, "r5" }, { PT_R6, "r6" }, { PT_R7, "r7" },
 379         { PT_B1, "b1" }, { PT_B2, "b2" }, { PT_B3, "b3" },
 380         { PT_B4, "b4" }, { PT_B5, "b5" },
 381         { PT_AR_EC, "ar.ec" }, { PT_AR_LC, "ar.lc" },
 382         /* pt_regs */
 383         { PT_CR_IPSR, "psr" }, { PT_CR_IIP, "ip" },
 384         { PT_CFM, "cfm" }, { PT_AR_UNAT, "ar.unat" },
 385         { PT_AR_PFS, "ar.pfs" }, { PT_AR_RSC, "ar.rsc" },
 386         { PT_AR_RNAT, "ar.rnat" }, { PT_AR_BSPSTORE, "ar.bspstore" },
 387         { PT_PR, "pr" }, { PT_B6, "b6" }, { PT_AR_BSP, "ar.bsp" },
 388         { PT_R1, "r1" }, { PT_R2, "r2" }, { PT_R3, "r3" },
 389         { PT_R12, "r12" }, { PT_R13, "r13" }, { PT_R14, "r14" },
 390         { PT_R15, "r15" }, { PT_R8, "r8" }, { PT_R9, "r9" },
 391         { PT_R10, "r10" }, { PT_R11, "r11" }, { PT_R16, "r16" },
 392         { PT_R17, "r17" }, { PT_R18, "r18" }, { PT_R19, "r19" },
 393         { PT_R20, "r20" }, { PT_R21, "r21" }, { PT_R22, "r22" },
 394         { PT_R23, "r23" }, { PT_R24, "r24" }, { PT_R25, "r25" },
 395         { PT_R26, "r26" }, { PT_R27, "r27" }, { PT_R28, "r28" },
 396         { PT_R29, "r29" }, { PT_R30, "r30" }, { PT_R31, "r31" },
 397         { PT_AR_CCV, "ar.ccv" }, { PT_AR_FPSR, "ar.fpsr" },
 398         { PT_B0, "b0" }, { PT_B7, "b7" }, { PT_F6, "f6" },
 399         { PT_F7, "f7" }, { PT_F8, "f8" }, { PT_F9, "f9" },
 400 # ifdef PT_AR_CSD
 401         { PT_AR_CSD, "ar.csd" },
 402 # endif
 403 # ifdef PT_AR_SSD
 404         { PT_AR_SSD, "ar.ssd" },
 405 # endif
 406         { PT_DBR, "dbr" }, { PT_IBR, "ibr" }, { PT_PMD, "pmd" },
 407 #elif defined(I386)
 408         XLAT(4*EBX),
 409         XLAT(4*ECX),
 410         XLAT(4*EDX),
 411         XLAT(4*ESI),
 412         XLAT(4*EDI),
 413         XLAT(4*EBP),
 414         XLAT(4*EAX),
 415         XLAT(4*DS),
 416         XLAT(4*ES),
 417         XLAT(4*FS),
 418         XLAT(4*GS),
 419         XLAT(4*ORIG_EAX),
 420         XLAT(4*EIP),
 421         XLAT(4*CS),
 422         XLAT(4*EFL),
 423         XLAT(4*UESP),
 424         XLAT(4*SS),
 425 #elif defined(X86_64) || defined(X32)
 426         XLAT(8*R15),
 427         XLAT(8*R14),
 428         XLAT(8*R13),
 429         XLAT(8*R12),
 430         XLAT(8*RBP),
 431         XLAT(8*RBX),
 432         XLAT(8*R11),
 433         XLAT(8*R10),
 434         XLAT(8*R9),
 435         XLAT(8*R8),
 436         XLAT(8*RAX),
 437         XLAT(8*RCX),
 438         XLAT(8*RDX),
 439         XLAT(8*RSI),
 440         XLAT(8*RDI),
 441         XLAT(8*ORIG_RAX),
 442         XLAT(8*RIP),
 443         XLAT(8*CS),
 444         { 8*EFLAGS,             "8*EFL"                                 },
 445         XLAT(8*RSP),
 446         XLAT(8*SS),
 447 #elif defined(M68K)
 448         XLAT(4*PT_D1),
 449         XLAT(4*PT_D2),
 450         XLAT(4*PT_D3),
 451         XLAT(4*PT_D4),
 452         XLAT(4*PT_D5),
 453         XLAT(4*PT_D6),
 454         XLAT(4*PT_D7),
 455         XLAT(4*PT_A0),
 456         XLAT(4*PT_A1),
 457         XLAT(4*PT_A2),
 458         XLAT(4*PT_A3),
 459         XLAT(4*PT_A4),
 460         XLAT(4*PT_A5),
 461         XLAT(4*PT_A6),
 462         XLAT(4*PT_D0),
 463         XLAT(4*PT_USP),
 464         XLAT(4*PT_ORIG_D0),
 465         XLAT(4*PT_SR),
 466         XLAT(4*PT_PC),
 467 #elif defined(SH)
 468         XLAT(4*REG_REG0),
 469         { 4*(REG_REG0+1),       "4*REG_REG1"                            },
 470         { 4*(REG_REG0+2),       "4*REG_REG2"                            },
 471         { 4*(REG_REG0+3),       "4*REG_REG3"                            },
 472         { 4*(REG_REG0+4),       "4*REG_REG4"                            },
 473         { 4*(REG_REG0+5),       "4*REG_REG5"                            },
 474         { 4*(REG_REG0+6),       "4*REG_REG6"                            },
 475         { 4*(REG_REG0+7),       "4*REG_REG7"                            },
 476         { 4*(REG_REG0+8),       "4*REG_REG8"                            },
 477         { 4*(REG_REG0+9),       "4*REG_REG9"                            },
 478         { 4*(REG_REG0+10),      "4*REG_REG10"                           },
 479         { 4*(REG_REG0+11),      "4*REG_REG11"                           },
 480         { 4*(REG_REG0+12),      "4*REG_REG12"                           },
 481         { 4*(REG_REG0+13),      "4*REG_REG13"                           },
 482         { 4*(REG_REG0+14),      "4*REG_REG14"                           },
 483         XLAT(4*REG_REG15),
 484         XLAT(4*REG_PC),
 485         XLAT(4*REG_PR),
 486         XLAT(4*REG_SR),
 487         XLAT(4*REG_GBR),
 488         XLAT(4*REG_MACH),
 489         XLAT(4*REG_MACL),
 490         XLAT(4*REG_SYSCALL),
 491         XLAT(4*REG_FPUL),
 492         XLAT(4*REG_FPREG0),
 493         { 4*(REG_FPREG0+1),     "4*REG_FPREG1"                          },
 494         { 4*(REG_FPREG0+2),     "4*REG_FPREG2"                          },
 495         { 4*(REG_FPREG0+3),     "4*REG_FPREG3"                          },
 496         { 4*(REG_FPREG0+4),     "4*REG_FPREG4"                          },
 497         { 4*(REG_FPREG0+5),     "4*REG_FPREG5"                          },
 498         { 4*(REG_FPREG0+6),     "4*REG_FPREG6"                          },
 499         { 4*(REG_FPREG0+7),     "4*REG_FPREG7"                          },
 500         { 4*(REG_FPREG0+8),     "4*REG_FPREG8"                          },
 501         { 4*(REG_FPREG0+9),     "4*REG_FPREG9"                          },
 502         { 4*(REG_FPREG0+10),    "4*REG_FPREG10"                         },
 503         { 4*(REG_FPREG0+11),    "4*REG_FPREG11"                         },
 504         { 4*(REG_FPREG0+12),    "4*REG_FPREG12"                         },
 505         { 4*(REG_FPREG0+13),    "4*REG_FPREG13"                         },
 506         { 4*(REG_FPREG0+14),    "4*REG_FPREG14"                         },
 507         XLAT(4*REG_FPREG15),
 508 # ifdef REG_XDREG0
 509         XLAT(4*REG_XDREG0),
 510         { 4*(REG_XDREG0+2),     "4*REG_XDREG2"                          },
 511         { 4*(REG_XDREG0+4),     "4*REG_XDREG4"                          },
 512         { 4*(REG_XDREG0+6),     "4*REG_XDREG6"                          },
 513         { 4*(REG_XDREG0+8),     "4*REG_XDREG8"                          },
 514         { 4*(REG_XDREG0+10),    "4*REG_XDREG10"                         },
 515         { 4*(REG_XDREG0+12),    "4*REG_XDREG12"                         },
 516         XLAT(4*REG_XDREG14),
 517 # endif
 518         XLAT(4*REG_FPSCR),
 519 #elif defined(SH64)
 520         { 0,                    "PC(L)"                                 },
 521         { 4,                    "PC(U)"                                 },
 522         { 8,                    "SR(L)"                                 },
 523         { 12,                   "SR(U)"                                 },
 524         { 16,                   "syscall no.(L)"                        },
 525         { 20,                   "syscall_no.(U)"                        },
 526         { 24,                   "R0(L)"                                 },
 527         { 28,                   "R0(U)"                                 },
 528         { 32,                   "R1(L)"                                 },
 529         { 36,                   "R1(U)"                                 },
 530         { 40,                   "R2(L)"                                 },
 531         { 44,                   "R2(U)"                                 },
 532         { 48,                   "R3(L)"                                 },
 533         { 52,                   "R3(U)"                                 },
 534         { 56,                   "R4(L)"                                 },
 535         { 60,                   "R4(U)"                                 },
 536         { 64,                   "R5(L)"                                 },
 537         { 68,                   "R5(U)"                                 },
 538         { 72,                   "R6(L)"                                 },
 539         { 76,                   "R6(U)"                                 },
 540         { 80,                   "R7(L)"                                 },
 541         { 84,                   "R7(U)"                                 },
 542         { 88,                   "R8(L)"                                 },
 543         { 92,                   "R8(U)"                                 },
 544         { 96,                   "R9(L)"                                 },
 545         { 100,                  "R9(U)"                                 },
 546         { 104,                  "R10(L)"                                },
 547         { 108,                  "R10(U)"                                },
 548         { 112,                  "R11(L)"                                },
 549         { 116,                  "R11(U)"                                },
 550         { 120,                  "R12(L)"                                },
 551         { 124,                  "R12(U)"                                },
 552         { 128,                  "R13(L)"                                },
 553         { 132,                  "R13(U)"                                },
 554         { 136,                  "R14(L)"                                },
 555         { 140,                  "R14(U)"                                },
 556         { 144,                  "R15(L)"                                },
 557         { 148,                  "R15(U)"                                },
 558         { 152,                  "R16(L)"                                },
 559         { 156,                  "R16(U)"                                },
 560         { 160,                  "R17(L)"                                },
 561         { 164,                  "R17(U)"                                },
 562         { 168,                  "R18(L)"                                },
 563         { 172,                  "R18(U)"                                },
 564         { 176,                  "R19(L)"                                },
 565         { 180,                  "R19(U)"                                },
 566         { 184,                  "R20(L)"                                },
 567         { 188,                  "R20(U)"                                },
 568         { 192,                  "R21(L)"                                },
 569         { 196,                  "R21(U)"                                },
 570         { 200,                  "R22(L)"                                },
 571         { 204,                  "R22(U)"                                },
 572         { 208,                  "R23(L)"                                },
 573         { 212,                  "R23(U)"                                },
 574         { 216,                  "R24(L)"                                },
 575         { 220,                  "R24(U)"                                },
 576         { 224,                  "R25(L)"                                },
 577         { 228,                  "R25(U)"                                },
 578         { 232,                  "R26(L)"                                },
 579         { 236,                  "R26(U)"                                },
 580         { 240,                  "R27(L)"                                },
 581         { 244,                  "R27(U)"                                },
 582         { 248,                  "R28(L)"                                },
 583         { 252,                  "R28(U)"                                },
 584         { 256,                  "R29(L)"                                },
 585         { 260,                  "R29(U)"                                },
 586         { 264,                  "R30(L)"                                },
 587         { 268,                  "R30(U)"                                },
 588         { 272,                  "R31(L)"                                },
 589         { 276,                  "R31(U)"                                },
 590         { 280,                  "R32(L)"                                },
 591         { 284,                  "R32(U)"                                },
 592         { 288,                  "R33(L)"                                },
 593         { 292,                  "R33(U)"                                },
 594         { 296,                  "R34(L)"                                },
 595         { 300,                  "R34(U)"                                },
 596         { 304,                  "R35(L)"                                },
 597         { 308,                  "R35(U)"                                },
 598         { 312,                  "R36(L)"                                },
 599         { 316,                  "R36(U)"                                },
 600         { 320,                  "R37(L)"                                },
 601         { 324,                  "R37(U)"                                },
 602         { 328,                  "R38(L)"                                },
 603         { 332,                  "R38(U)"                                },
 604         { 336,                  "R39(L)"                                },
 605         { 340,                  "R39(U)"                                },
 606         { 344,                  "R40(L)"                                },
 607         { 348,                  "R40(U)"                                },
 608         { 352,                  "R41(L)"                                },
 609         { 356,                  "R41(U)"                                },
 610         { 360,                  "R42(L)"                                },
 611         { 364,                  "R42(U)"                                },
 612         { 368,                  "R43(L)"                                },
 613         { 372,                  "R43(U)"                                },
 614         { 376,                  "R44(L)"                                },
 615         { 380,                  "R44(U)"                                },
 616         { 384,                  "R45(L)"                                },
 617         { 388,                  "R45(U)"                                },
 618         { 392,                  "R46(L)"                                },
 619         { 396,                  "R46(U)"                                },
 620         { 400,                  "R47(L)"                                },
 621         { 404,                  "R47(U)"                                },
 622         { 408,                  "R48(L)"                                },
 623         { 412,                  "R48(U)"                                },
 624         { 416,                  "R49(L)"                                },
 625         { 420,                  "R49(U)"                                },
 626         { 424,                  "R50(L)"                                },
 627         { 428,                  "R50(U)"                                },
 628         { 432,                  "R51(L)"                                },
 629         { 436,                  "R51(U)"                                },
 630         { 440,                  "R52(L)"                                },
 631         { 444,                  "R52(U)"                                },
 632         { 448,                  "R53(L)"                                },
 633         { 452,                  "R53(U)"                                },
 634         { 456,                  "R54(L)"                                },
 635         { 460,                  "R54(U)"                                },
 636         { 464,                  "R55(L)"                                },
 637         { 468,                  "R55(U)"                                },
 638         { 472,                  "R56(L)"                                },
 639         { 476,                  "R56(U)"                                },
 640         { 480,                  "R57(L)"                                },
 641         { 484,                  "R57(U)"                                },
 642         { 488,                  "R58(L)"                                },
 643         { 492,                  "R58(U)"                                },
 644         { 496,                  "R59(L)"                                },
 645         { 500,                  "R59(U)"                                },
 646         { 504,                  "R60(L)"                                },
 647         { 508,                  "R60(U)"                                },
 648         { 512,                  "R61(L)"                                },
 649         { 516,                  "R61(U)"                                },
 650         { 520,                  "R62(L)"                                },
 651         { 524,                  "R62(U)"                                },
 652         { 528,                  "TR0(L)"                                },
 653         { 532,                  "TR0(U)"                                },
 654         { 536,                  "TR1(L)"                                },
 655         { 540,                  "TR1(U)"                                },
 656         { 544,                  "TR2(L)"                                },
 657         { 548,                  "TR2(U)"                                },
 658         { 552,                  "TR3(L)"                                },
 659         { 556,                  "TR3(U)"                                },
 660         { 560,                  "TR4(L)"                                },
 661         { 564,                  "TR4(U)"                                },
 662         { 568,                  "TR5(L)"                                },
 663         { 572,                  "TR5(U)"                                },
 664         { 576,                  "TR6(L)"                                },
 665         { 580,                  "TR6(U)"                                },
 666         { 584,                  "TR7(L)"                                },
 667         { 588,                  "TR7(U)"                                },
 668         /* This entry is in case pt_regs contains dregs (depends on
 669            the kernel build options). */
 670         { uoff(regs),           "offsetof(struct user, regs)"           },
 671         { uoff(fpu),            "offsetof(struct user, fpu)"            },
 672 #elif defined(ARM)
 673         { uoff(regs.ARM_r0),    "r0"                                    },
 674         { uoff(regs.ARM_r1),    "r1"                                    },
 675         { uoff(regs.ARM_r2),    "r2"                                    },
 676         { uoff(regs.ARM_r3),    "r3"                                    },
 677         { uoff(regs.ARM_r4),    "r4"                                    },
 678         { uoff(regs.ARM_r5),    "r5"                                    },
 679         { uoff(regs.ARM_r6),    "r6"                                    },
 680         { uoff(regs.ARM_r7),    "r7"                                    },
 681         { uoff(regs.ARM_r8),    "r8"                                    },
 682         { uoff(regs.ARM_r9),    "r9"                                    },
 683         { uoff(regs.ARM_r10),   "r10"                                   },
 684         { uoff(regs.ARM_fp),    "fp"                                    },
 685         { uoff(regs.ARM_ip),    "ip"                                    },
 686         { uoff(regs.ARM_sp),    "sp"                                    },
 687         { uoff(regs.ARM_lr),    "lr"                                    },
 688         { uoff(regs.ARM_pc),    "pc"                                    },
 689         { uoff(regs.ARM_cpsr),  "cpsr"                                  },
 690 #elif defined(AVR32)
 691         { uoff(regs.sr),        "sr"                                    },
 692         { uoff(regs.pc),        "pc"                                    },
 693         { uoff(regs.lr),        "lr"                                    },
 694         { uoff(regs.sp),        "sp"                                    },
 695         { uoff(regs.r12),       "r12"                                   },
 696         { uoff(regs.r11),       "r11"                                   },
 697         { uoff(regs.r10),       "r10"                                   },
 698         { uoff(regs.r9),        "r9"                                    },
 699         { uoff(regs.r8),        "r8"                                    },
 700         { uoff(regs.r7),        "r7"                                    },
 701         { uoff(regs.r6),        "r6"                                    },
 702         { uoff(regs.r5),        "r5"                                    },
 703         { uoff(regs.r4),        "r4"                                    },
 704         { uoff(regs.r3),        "r3"                                    },
 705         { uoff(regs.r2),        "r2"                                    },
 706         { uoff(regs.r1),        "r1"                                    },
 707         { uoff(regs.r0),        "r0"                                    },
 708         { uoff(regs.r12_orig),  "orig_r12"                              },
 709 #elif defined(MIPS)
 710         { 0,                    "r0"                                    },
 711         { 1,                    "r1"                                    },
 712         { 2,                    "r2"                                    },
 713         { 3,                    "r3"                                    },
 714         { 4,                    "r4"                                    },
 715         { 5,                    "r5"                                    },
 716         { 6,                    "r6"                                    },
 717         { 7,                    "r7"                                    },
 718         { 8,                    "r8"                                    },
 719         { 9,                    "r9"                                    },
 720         { 10,                   "r10"                                   },
 721         { 11,                   "r11"                                   },
 722         { 12,                   "r12"                                   },
 723         { 13,                   "r13"                                   },
 724         { 14,                   "r14"                                   },
 725         { 15,                   "r15"                                   },
 726         { 16,                   "r16"                                   },
 727         { 17,                   "r17"                                   },
 728         { 18,                   "r18"                                   },
 729         { 19,                   "r19"                                   },
 730         { 20,                   "r20"                                   },
 731         { 21,                   "r21"                                   },
 732         { 22,                   "r22"                                   },
 733         { 23,                   "r23"                                   },
 734         { 24,                   "r24"                                   },
 735         { 25,                   "r25"                                   },
 736         { 26,                   "r26"                                   },
 737         { 27,                   "r27"                                   },
 738         { 28,                   "r28"                                   },
 739         { 29,                   "r29"                                   },
 740         { 30,                   "r30"                                   },
 741         { 31,                   "r31"                                   },
 742         { 32,                   "f0"                                    },
 743         { 33,                   "f1"                                    },
 744         { 34,                   "f2"                                    },
 745         { 35,                   "f3"                                    },
 746         { 36,                   "f4"                                    },
 747         { 37,                   "f5"                                    },
 748         { 38,                   "f6"                                    },
 749         { 39,                   "f7"                                    },
 750         { 40,                   "f8"                                    },
 751         { 41,                   "f9"                                    },
 752         { 42,                   "f10"                                   },
 753         { 43,                   "f11"                                   },
 754         { 44,                   "f12"                                   },
 755         { 45,                   "f13"                                   },
 756         { 46,                   "f14"                                   },
 757         { 47,                   "f15"                                   },
 758         { 48,                   "f16"                                   },
 759         { 49,                   "f17"                                   },
 760         { 50,                   "f18"                                   },
 761         { 51,                   "f19"                                   },
 762         { 52,                   "f20"                                   },
 763         { 53,                   "f21"                                   },
 764         { 54,                   "f22"                                   },
 765         { 55,                   "f23"                                   },
 766         { 56,                   "f24"                                   },
 767         { 57,                   "f25"                                   },
 768         { 58,                   "f26"                                   },
 769         { 59,                   "f27"                                   },
 770         { 60,                   "f28"                                   },
 771         { 61,                   "f29"                                   },
 772         { 62,                   "f30"                                   },
 773         { 63,                   "f31"                                   },
 774         { 64,                   "pc"                                    },
 775         { 65,                   "cause"                                 },
 776         { 66,                   "badvaddr"                              },
 777         { 67,                   "mmhi"                                  },
 778         { 68,                   "mmlo"                                  },
 779         { 69,                   "fpcsr"                                 },
 780         { 70,                   "fpeir"                                 },
 781 #elif defined(TILE)
 782         { PTREGS_OFFSET_REG(0),  "r0"  },
 783         { PTREGS_OFFSET_REG(1),  "r1"  },
 784         { PTREGS_OFFSET_REG(2),  "r2"  },
 785         { PTREGS_OFFSET_REG(3),  "r3"  },
 786         { PTREGS_OFFSET_REG(4),  "r4"  },
 787         { PTREGS_OFFSET_REG(5),  "r5"  },
 788         { PTREGS_OFFSET_REG(6),  "r6"  },
 789         { PTREGS_OFFSET_REG(7),  "r7"  },
 790         { PTREGS_OFFSET_REG(8),  "r8"  },
 791         { PTREGS_OFFSET_REG(9),  "r9"  },
 792         { PTREGS_OFFSET_REG(10), "r10" },
 793         { PTREGS_OFFSET_REG(11), "r11" },
 794         { PTREGS_OFFSET_REG(12), "r12" },
 795         { PTREGS_OFFSET_REG(13), "r13" },
 796         { PTREGS_OFFSET_REG(14), "r14" },
 797         { PTREGS_OFFSET_REG(15), "r15" },
 798         { PTREGS_OFFSET_REG(16), "r16" },
 799         { PTREGS_OFFSET_REG(17), "r17" },
 800         { PTREGS_OFFSET_REG(18), "r18" },
 801         { PTREGS_OFFSET_REG(19), "r19" },
 802         { PTREGS_OFFSET_REG(20), "r20" },
 803         { PTREGS_OFFSET_REG(21), "r21" },
 804         { PTREGS_OFFSET_REG(22), "r22" },
 805         { PTREGS_OFFSET_REG(23), "r23" },
 806         { PTREGS_OFFSET_REG(24), "r24" },
 807         { PTREGS_OFFSET_REG(25), "r25" },
 808         { PTREGS_OFFSET_REG(26), "r26" },
 809         { PTREGS_OFFSET_REG(27), "r27" },
 810         { PTREGS_OFFSET_REG(28), "r28" },
 811         { PTREGS_OFFSET_REG(29), "r29" },
 812         { PTREGS_OFFSET_REG(30), "r30" },
 813         { PTREGS_OFFSET_REG(31), "r31" },
 814         { PTREGS_OFFSET_REG(32), "r32" },
 815         { PTREGS_OFFSET_REG(33), "r33" },
 816         { PTREGS_OFFSET_REG(34), "r34" },
 817         { PTREGS_OFFSET_REG(35), "r35" },
 818         { PTREGS_OFFSET_REG(36), "r36" },
 819         { PTREGS_OFFSET_REG(37), "r37" },
 820         { PTREGS_OFFSET_REG(38), "r38" },
 821         { PTREGS_OFFSET_REG(39), "r39" },
 822         { PTREGS_OFFSET_REG(40), "r40" },
 823         { PTREGS_OFFSET_REG(41), "r41" },
 824         { PTREGS_OFFSET_REG(42), "r42" },
 825         { PTREGS_OFFSET_REG(43), "r43" },
 826         { PTREGS_OFFSET_REG(44), "r44" },
 827         { PTREGS_OFFSET_REG(45), "r45" },
 828         { PTREGS_OFFSET_REG(46), "r46" },
 829         { PTREGS_OFFSET_REG(47), "r47" },
 830         { PTREGS_OFFSET_REG(48), "r48" },
 831         { PTREGS_OFFSET_REG(49), "r49" },
 832         { PTREGS_OFFSET_REG(50), "r50" },
 833         { PTREGS_OFFSET_REG(51), "r51" },
 834         { PTREGS_OFFSET_REG(52), "r52" },
 835         { PTREGS_OFFSET_TP, "tp" },
 836         { PTREGS_OFFSET_SP, "sp" },
 837         { PTREGS_OFFSET_LR, "lr" },
 838         { PTREGS_OFFSET_PC, "pc" },
 839         { PTREGS_OFFSET_EX1, "ex1" },
 840         { PTREGS_OFFSET_FAULTNUM, "faultnum" },
 841         { PTREGS_OFFSET_ORIG_R0, "orig_r0" },
 842         { PTREGS_OFFSET_FLAGS, "flags" },
 843 #endif
 844 #ifdef CRISV10
 845         XLAT(4*PT_FRAMETYPE),
 846         XLAT(4*PT_ORIG_R10),
 847         XLAT(4*PT_R13),
 848         XLAT(4*PT_R12),
 849         XLAT(4*PT_R11),
 850         XLAT(4*PT_R10),
 851         XLAT(4*PT_R9),
 852         XLAT(4*PT_R8),
 853         XLAT(4*PT_R7),
 854         XLAT(4*PT_R6),
 855         XLAT(4*PT_R5),
 856         XLAT(4*PT_R4),
 857         XLAT(4*PT_R3),
 858         XLAT(4*PT_R2),
 859         XLAT(4*PT_R1),
 860         XLAT(4*PT_R0),
 861         XLAT(4*PT_MOF),
 862         XLAT(4*PT_DCCR),
 863         XLAT(4*PT_SRP),
 864         XLAT(4*PT_IRP),
 865         XLAT(4*PT_CSRINSTR),
 866         XLAT(4*PT_CSRADDR),
 867         XLAT(4*PT_CSRDATA),
 868         XLAT(4*PT_USP),
 869 #endif
 870 #ifdef CRISV32
 871         XLAT(4*PT_ORIG_R10),
 872         XLAT(4*PT_R0),
 873         XLAT(4*PT_R1),
 874         XLAT(4*PT_R2),
 875         XLAT(4*PT_R3),
 876         XLAT(4*PT_R4),
 877         XLAT(4*PT_R5),
 878         XLAT(4*PT_R6),
 879         XLAT(4*PT_R7),
 880         XLAT(4*PT_R8),
 881         XLAT(4*PT_R9),
 882         XLAT(4*PT_R10),
 883         XLAT(4*PT_R11),
 884         XLAT(4*PT_R12),
 885         XLAT(4*PT_R13),
 886         XLAT(4*PT_ACR),
 887         XLAT(4*PT_SRS),
 888         XLAT(4*PT_MOF),
 889         XLAT(4*PT_SPC),
 890         XLAT(4*PT_CCS),
 891         XLAT(4*PT_SRP),
 892         XLAT(4*PT_ERP),
 893         XLAT(4*PT_EXS),
 894         XLAT(4*PT_EDA),
 895         XLAT(4*PT_USP),
 896         XLAT(4*PT_PPC),
 897         XLAT(4*PT_BP_CTRL),
 898         XLAT(4*PT_BP+4),
 899         XLAT(4*PT_BP+8),
 900         XLAT(4*PT_BP+12),
 901         XLAT(4*PT_BP+16),
 902         XLAT(4*PT_BP+20),
 903         XLAT(4*PT_BP+24),
 904         XLAT(4*PT_BP+28),
 905         XLAT(4*PT_BP+32),
 906         XLAT(4*PT_BP+36),
 907         XLAT(4*PT_BP+40),
 908         XLAT(4*PT_BP+44),
 909         XLAT(4*PT_BP+48),
 910         XLAT(4*PT_BP+52),
 911         XLAT(4*PT_BP+56),
 912 #endif
 913 #ifdef MICROBLAZE
 914         { PT_GPR(0),            "r0"                                    },
 915         { PT_GPR(1),            "r1"                                    },
 916         { PT_GPR(2),            "r2"                                    },
 917         { PT_GPR(3),            "r3"                                    },
 918         { PT_GPR(4),            "r4"                                    },
 919         { PT_GPR(5),            "r5"                                    },
 920         { PT_GPR(6),            "r6"                                    },
 921         { PT_GPR(7),            "r7"                                    },
 922         { PT_GPR(8),            "r8"                                    },
 923         { PT_GPR(9),            "r9"                                    },
 924         { PT_GPR(10),           "r10"                                   },
 925         { PT_GPR(11),           "r11"                                   },
 926         { PT_GPR(12),           "r12"                                   },
 927         { PT_GPR(13),           "r13"                                   },
 928         { PT_GPR(14),           "r14"                                   },
 929         { PT_GPR(15),           "r15"                                   },
 930         { PT_GPR(16),           "r16"                                   },
 931         { PT_GPR(17),           "r17"                                   },
 932         { PT_GPR(18),           "r18"                                   },
 933         { PT_GPR(19),           "r19"                                   },
 934         { PT_GPR(20),           "r20"                                   },
 935         { PT_GPR(21),           "r21"                                   },
 936         { PT_GPR(22),           "r22"                                   },
 937         { PT_GPR(23),           "r23"                                   },
 938         { PT_GPR(24),           "r24"                                   },
 939         { PT_GPR(25),           "r25"                                   },
 940         { PT_GPR(26),           "r26"                                   },
 941         { PT_GPR(27),           "r27"                                   },
 942         { PT_GPR(28),           "r28"                                   },
 943         { PT_GPR(29),           "r29"                                   },
 944         { PT_GPR(30),           "r30"                                   },
 945         { PT_GPR(31),           "r31"                                   },
 946         { PT_PC,                "rpc",                                  },
 947         { PT_MSR,               "rmsr",                                 },
 948         { PT_EAR,               "rear",                                 },
 949         { PT_ESR,               "resr",                                 },
 950         { PT_FSR,               "rfsr",                                 },
 951         { PT_KERNEL_MODE,       "kernel_mode",                          },
 952 #endif
 953 #ifdef OR1K
 954         { 4*0,  "r0" },
 955         { 4*1,  "r1" },
 956         { 4*2,  "r2" },
 957         { 4*3,  "r3" },
 958         { 4*4,  "r4" },
 959         { 4*5,  "r5" },
 960         { 4*6,  "r6" },
 961         { 4*7,  "r7" },
 962         { 4*8,  "r8" },
 963         { 4*9,  "r9" },
 964         { 4*10, "r10" },
 965         { 4*11, "r11" },
 966         { 4*12, "r12" },
 967         { 4*13, "r13" },
 968         { 4*14, "r14" },
 969         { 4*15, "r15" },
 970         { 4*16, "r16" },
 971         { 4*17, "r17" },
 972         { 4*18, "r18" },
 973         { 4*19, "r19" },
 974         { 4*20, "r20" },
 975         { 4*21, "r21" },
 976         { 4*22, "r22" },
 977         { 4*23, "r23" },
 978         { 4*24, "r24" },
 979         { 4*25, "r25" },
 980         { 4*26, "r26" },
 981         { 4*27, "r27" },
 982         { 4*28, "r28" },
 983         { 4*29, "r29" },
 984         { 4*30, "r30" },
 985         { 4*31, "r31" },
 986         { 4*32, "pc" },
 987         { 4*33, "sr" },
 988 #endif
 989 #ifdef XTENSA
 990         { REG_A_BASE,           "a0"            },
 991         { REG_A_BASE+1,         "a1"            },
 992         { REG_A_BASE+2,         "a2"            },
 993         { REG_A_BASE+3,         "a3"            },
 994         { REG_A_BASE+4,         "a4"            },
 995         { REG_A_BASE+5,         "a5"            },
 996         { REG_A_BASE+6,         "a6"            },
 997         { REG_A_BASE+7,         "a7"            },
 998         { REG_A_BASE+8,         "a8"            },
 999         { REG_A_BASE+9,         "a9"            },
1000         { REG_A_BASE+10,        "a10"           },
1001         { REG_A_BASE+11,        "a11"           },
1002         { REG_A_BASE+12,        "a12"           },
1003         { REG_A_BASE+13,        "a13"           },
1004         { REG_A_BASE+14,        "a14"           },
1005         { REG_A_BASE+15,        "a15"           },
1006         { REG_PC,               "pc"            },
1007         { SYSCALL_NR,           "syscall_nr"    },
1008         { REG_AR_BASE,          "ar0"           },
1009         { REG_AR_BASE+1,        "ar1"           },
1010         { REG_AR_BASE+2,        "ar2"           },
1011         { REG_AR_BASE+3,        "ar3"           },
1012         { REG_AR_BASE+4,        "ar4"           },
1013         { REG_AR_BASE+5,        "ar5"           },
1014         { REG_AR_BASE+6,        "ar6"           },
1015         { REG_AR_BASE+7,        "ar7"           },
1016         { REG_AR_BASE+8,        "ar8"           },
1017         { REG_AR_BASE+9,        "ar9"           },
1018         { REG_AR_BASE+10,       "ar10"          },
1019         { REG_AR_BASE+11,       "ar11"          },
1020         { REG_AR_BASE+12,       "ar12"          },
1021         { REG_AR_BASE+13,       "ar13"          },
1022         { REG_AR_BASE+14,       "ar14"          },
1023         { REG_AR_BASE+15,       "ar15"          },
1024         { REG_AR_BASE+16,       "ar16"          },
1025         { REG_AR_BASE+17,       "ar17"          },
1026         { REG_AR_BASE+18,       "ar18"          },
1027         { REG_AR_BASE+19,       "ar19"          },
1028         { REG_AR_BASE+20,       "ar20"          },
1029         { REG_AR_BASE+21,       "ar21"          },
1030         { REG_AR_BASE+22,       "ar22"          },
1031         { REG_AR_BASE+23,       "ar23"          },
1032         { REG_AR_BASE+24,       "ar24"          },
1033         { REG_AR_BASE+25,       "ar25"          },
1034         { REG_AR_BASE+26,       "ar26"          },
1035         { REG_AR_BASE+27,       "ar27"          },
1036         { REG_AR_BASE+28,       "ar28"          },
1037         { REG_AR_BASE+29,       "ar29"          },
1038         { REG_AR_BASE+30,       "ar30"          },
1039         { REG_AR_BASE+31,       "ar31"          },
1040         { REG_AR_BASE+32,       "ar32"          },
1041         { REG_AR_BASE+33,       "ar33"          },
1042         { REG_AR_BASE+34,       "ar34"          },
1043         { REG_AR_BASE+35,       "ar35"          },
1044         { REG_AR_BASE+36,       "ar36"          },
1045         { REG_AR_BASE+37,       "ar37"          },
1046         { REG_AR_BASE+38,       "ar38"          },
1047         { REG_AR_BASE+39,       "ar39"          },
1048         { REG_AR_BASE+40,       "ar40"          },
1049         { REG_AR_BASE+41,       "ar41"          },
1050         { REG_AR_BASE+42,       "ar42"          },
1051         { REG_AR_BASE+43,       "ar43"          },
1052         { REG_AR_BASE+44,       "ar44"          },
1053         { REG_AR_BASE+45,       "ar45"          },
1054         { REG_AR_BASE+46,       "ar46"          },
1055         { REG_AR_BASE+47,       "ar47"          },
1056         { REG_AR_BASE+48,       "ar48"          },
1057         { REG_AR_BASE+49,       "ar49"          },
1058         { REG_AR_BASE+50,       "ar50"          },
1059         { REG_AR_BASE+51,       "ar51"          },
1060         { REG_AR_BASE+52,       "ar52"          },
1061         { REG_AR_BASE+53,       "ar53"          },
1062         { REG_AR_BASE+54,       "ar54"          },
1063         { REG_AR_BASE+55,       "ar55"          },
1064         { REG_AR_BASE+56,       "ar56"          },
1065         { REG_AR_BASE+57,       "ar57"          },
1066         { REG_AR_BASE+58,       "ar58"          },
1067         { REG_AR_BASE+59,       "ar59"          },
1068         { REG_AR_BASE+60,       "ar60"          },
1069         { REG_AR_BASE+61,       "ar61"          },
1070         { REG_AR_BASE+62,       "ar62"          },
1071         { REG_AR_BASE+63,       "ar63"          },
1072         { REG_LBEG,             "lbeg"          },
1073         { REG_LEND,             "lend"          },
1074         { REG_LCOUNT,           "lcount"        },
1075         { REG_SAR,              "sar"           },
1076         { REG_WB,               "wb"            },
1077         { REG_WS,               "ws"            },
1078         { REG_PS,               "ps"            },
1079 #endif
1080
1081         /* Other fields in "struct user" */
1082 #if defined(S390) || defined(S390X)
1083         { uoff(u_tsize),        "offsetof(struct user, u_tsize)"        },
1084         { uoff(u_dsize),        "offsetof(struct user, u_dsize)"        },
1085         { uoff(u_ssize),        "offsetof(struct user, u_ssize)"        },
1086         { uoff(start_code),     "offsetof(struct user, start_code)"     },
1087         /* S390[X] has no start_data */
1088         { uoff(start_stack),    "offsetof(struct user, start_stack)"    },
1089         { uoff(signal),         "offsetof(struct user, signal)"         },
1090         { uoff(u_ar0),          "offsetof(struct user, u_ar0)"          },
1091         { uoff(magic),          "offsetof(struct user, magic)"          },
1092         { uoff(u_comm),         "offsetof(struct user, u_comm)"         },
1093         { sizeof(struct user),  "sizeof(struct user)"                   },
1094 #elif defined(POWERPC)
1095         { sizeof(struct user),  "sizeof(struct user)"                   },
1096 #elif defined(I386) || defined(X86_64) || defined(X32)
1097         { uoff(u_fpvalid),      "offsetof(struct user, u_fpvalid)"      },
1098         { uoff(i387),           "offsetof(struct user, i387)"           },
1099         { uoff(u_tsize),        "offsetof(struct user, u_tsize)"        },
1100         { uoff(u_dsize),        "offsetof(struct user, u_dsize)"        },
1101         { uoff(u_ssize),        "offsetof(struct user, u_ssize)"        },
1102         { uoff(start_code),     "offsetof(struct user, start_code)"     },
1103         { uoff(start_stack),    "offsetof(struct user, start_stack)"    },
1104         { uoff(signal),         "offsetof(struct user, signal)"         },
1105         { uoff(reserved),       "offsetof(struct user, reserved)"       },
1106         { uoff(u_ar0),          "offsetof(struct user, u_ar0)"          },
1107         { uoff(u_fpstate),      "offsetof(struct user, u_fpstate)"      },
1108         { uoff(magic),          "offsetof(struct user, magic)"          },
1109         { uoff(u_comm),         "offsetof(struct user, u_comm)"         },
1110         { uoff(u_debugreg),     "offsetof(struct user, u_debugreg)"     },
1111         { sizeof(struct user),  "sizeof(struct user)"                   },
1112 #elif defined(IA64)
1113         { sizeof(struct user),  "sizeof(struct user)"                   },
1114 #elif defined(ARM)
1115         { uoff(u_fpvalid),      "offsetof(struct user, u_fpvalid)"      },
1116         { uoff(u_tsize),        "offsetof(struct user, u_tsize)"        },
1117         { uoff(u_dsize),        "offsetof(struct user, u_dsize)"        },
1118         { uoff(u_ssize),        "offsetof(struct user, u_ssize)"        },
1119         { uoff(start_code),     "offsetof(struct user, start_code)"     },
1120         { uoff(start_stack),    "offsetof(struct user, start_stack)"    },
1121         { uoff(signal),         "offsetof(struct user, signal)"         },
1122         { uoff(reserved),       "offsetof(struct user, reserved)"       },
1123         { uoff(u_ar0),          "offsetof(struct user, u_ar0)"          },
1124         { uoff(magic),          "offsetof(struct user, magic)"          },
1125         { uoff(u_comm),         "offsetof(struct user, u_comm)"         },
1126         { sizeof(struct user),  "sizeof(struct user)"                   },
1127 #elif defined(AARCH64)
1128         /* nothing */
1129 #elif defined(M68K)
1130         { uoff(u_fpvalid),      "offsetof(struct user, u_fpvalid)"      },
1131         { uoff(m68kfp),         "offsetof(struct user, m68kfp)"         },
1132         { uoff(u_tsize),        "offsetof(struct user, u_tsize)"        },
1133         { uoff(u_dsize),        "offsetof(struct user, u_dsize)"        },
1134         { uoff(u_ssize),        "offsetof(struct user, u_ssize)"        },
1135         { uoff(start_code),     "offsetof(struct user, start_code)"     },
1136         { uoff(start_stack),    "offsetof(struct user, start_stack)"    },
1137         { uoff(signal),         "offsetof(struct user, signal)"         },
1138         { uoff(reserved),       "offsetof(struct user, reserved)"       },
1139         { uoff(u_ar0),          "offsetof(struct user, u_ar0)"          },
1140         { uoff(u_fpstate),      "offsetof(struct user, u_fpstate)"      },
1141         { uoff(magic),          "offsetof(struct user, magic)"          },
1142         { uoff(u_comm),         "offsetof(struct user, u_comm)"         },
1143         { sizeof(struct user),  "sizeof(struct user)"                   },
1144 #elif defined(MIPS) || defined(LINUX_MIPSN32)
1145         { uoff(u_tsize),        "offsetof(struct user, u_tsize)"        },
1146         { uoff(u_dsize),        "offsetof(struct user, u_dsize)"        },
1147         { uoff(u_ssize),        "offsetof(struct user, u_ssize)"        },
1148         { uoff(start_code),     "offsetof(struct user, start_code)"     },
1149         { uoff(start_data),     "offsetof(struct user, start_data)"     },
1150         { uoff(start_stack),    "offsetof(struct user, start_stack)"    },
1151         { uoff(signal),         "offsetof(struct user, signal)"         },
1152         { uoff(u_ar0),          "offsetof(struct user, u_ar0)"          },
1153         { uoff(magic),          "offsetof(struct user, magic)"          },
1154         { uoff(u_comm),         "offsetof(struct user, u_comm)"         },
1155         { sizeof(struct user),  "sizeof(struct user)"                   },
1156 #elif defined(ALPHA)
1157         { sizeof(struct user),  "sizeof(struct user)"                   },
1158 #elif defined(SPARC)
1159         { sizeof(struct user),  "sizeof(struct user)"                   },
1160 #elif defined(SPARC64)
1161         { uoff(u_tsize),        "offsetof(struct user, u_tsize)"        },
1162         { uoff(u_dsize),        "offsetof(struct user, u_dsize)"        },
1163         { uoff(u_ssize),        "offsetof(struct user, u_ssize)"        },
1164         { uoff(signal),         "offsetof(struct user, signal)"         },
1165         { uoff(magic),          "offsetof(struct user, magic)"          },
1166         { uoff(u_comm),         "offsetof(struct user, u_comm)"         },
1167         { sizeof(struct user),  "sizeof(struct user)"                   },
1168 #elif defined(HPPA)
1169         /* nothing */
1170 #elif defined(SH) || defined(SH64)
1171         { uoff(u_fpvalid),      "offsetof(struct user, u_fpvalid)"      },
1172         { uoff(u_tsize),        "offsetof(struct user, u_tsize)"        },
1173         { uoff(u_dsize),        "offsetof(struct user, u_dsize)"        },
1174         { uoff(u_ssize),        "offsetof(struct user, u_ssize)"        },
1175         { uoff(start_code),     "offsetof(struct user, start_code)"     },
1176         { uoff(start_data),     "offsetof(struct user, start_data)"     },
1177         { uoff(start_stack),    "offsetof(struct user, start_stack)"    },
1178         { uoff(signal),         "offsetof(struct user, signal)"         },
1179         { uoff(u_ar0),          "offsetof(struct user, u_ar0)"          },
1180         { uoff(u_fpstate),      "offsetof(struct user, u_fpstate)"      },
1181         { uoff(magic),          "offsetof(struct user, magic)"          },
1182         { uoff(u_comm),         "offsetof(struct user, u_comm)"         },
1183         { sizeof(struct user),  "sizeof(struct user)"                   },
1184 #elif defined(CRISV10) || defined(CRISV32)
1185         { sizeof(struct user),  "sizeof(struct user)"                   },
1186 #elif defined(TILE)
1187         /* nothing */
1188 #elif defined(MICROBLAZE)
1189         { sizeof(struct user),  "sizeof(struct user)"                   },
1190 #elif defined(AVR32)
1191         { uoff(u_tsize),        "offsetof(struct user, u_tsize)"        },
1192         { uoff(u_dsize),        "offsetof(struct user, u_dsize)"        },
1193         { uoff(u_ssize),        "offsetof(struct user, u_ssize)"        },
1194         { uoff(start_code),     "offsetof(struct user, start_code)"     },
1195         { uoff(start_data),     "offsetof(struct user, start_data)"     },
1196         { uoff(start_stack),    "offsetof(struct user, start_stack)"    },
1197         { uoff(signal),         "offsetof(struct user, signal)"         },
1198         { uoff(u_ar0),          "offsetof(struct user, u_ar0)"          },
1199         { uoff(magic),          "offsetof(struct user, magic)"          },
1200         { uoff(u_comm),         "offsetof(struct user, u_comm)"         },
1201         { sizeof(struct user),  "sizeof(struct user)"                   },
1202 #elif defined(BFIN)
1203         { uoff(u_tsize),        "offsetof(struct user, u_tsize)"        },
1204         { uoff(u_dsize),        "offsetof(struct user, u_dsize)"        },
1205         { uoff(u_ssize),        "offsetof(struct user, u_ssize)"        },
1206         { uoff(start_code),     "offsetof(struct user, start_code)"     },
1207         { uoff(signal),         "offsetof(struct user, signal)"         },
1208         { uoff(u_ar0),          "offsetof(struct user, u_ar0)"          },
1209         { uoff(magic),          "offsetof(struct user, magic)"          },
1210         { uoff(u_comm),         "offsetof(struct user, u_comm)"         },
1211         { sizeof(struct user),  "sizeof(struct user)"                   },
1212 #elif defined(OR1K)
1213         /* nothing */
1214 #elif defined(METAG)
1215         /* nothing */
1216 #elif defined(XTENSA)
1217         /* nothing */
1218 #elif defined(ARC)
1219         /* nothing */
1220 #endif
1221         XLAT_END
1222 };
1223
1224 int
1225 sys_ptrace(struct tcb *tcp)
1226 {
1227         const struct xlat *x;
1228         unsigned long addr;
1229
1230         if (entering(tcp)) {
1231                 printxval(ptrace_cmds, tcp->u_arg[0], "PTRACE_???");
1232                 tprintf(", %lu, ", tcp->u_arg[1]);
1233
1234                 addr = tcp->u_arg[2];
1235                 if (tcp->u_arg[0] == PTRACE_PEEKUSER
1236                  || tcp->u_arg[0] == PTRACE_POKEUSER
1237                 ) {
1238                         for (x = struct_user_offsets; x->str; x++) {
1239                                 if (x->val >= addr)
1240                                         break;
1241                         }
1242                         if (!x->str)
1243                                 tprintf("%#lx, ", addr);
1244                         else if (x->val > addr && x != struct_user_offsets) {
1245                                 x--;
1246                                 tprintf("%s + %ld, ", x->str, addr - x->val);
1247                         }
1248                         else
1249                                 tprintf("%s, ", x->str);
1250                 } else
1251 #ifdef PTRACE_GETREGSET
1252                 if (tcp->u_arg[0] == PTRACE_GETREGSET
1253                  || tcp->u_arg[0] == PTRACE_SETREGSET
1254                 ) {
1255                         printxval(nt_descriptor_types, tcp->u_arg[2], "NT_???");
1256                         tprints(", ");
1257                 } else
1258 #endif
1259                         tprintf("%#lx, ", addr);
1260
1261
1262                 switch (tcp->u_arg[0]) {
1263 #ifndef IA64
1264                 case PTRACE_PEEKDATA:
1265                 case PTRACE_PEEKTEXT:
1266                 case PTRACE_PEEKUSER:
1267                         break;
1268 #endif
1269                 case PTRACE_CONT:
1270                 case PTRACE_SINGLESTEP:
1271                 case PTRACE_SYSCALL:
1272                 case PTRACE_DETACH:
1273                         printsignal(tcp->u_arg[3]);
1274                         break;
1275 #ifdef PTRACE_SETOPTIONS
1276                 case PTRACE_SETOPTIONS:
1277                         printflags(ptrace_setoptions_flags, tcp->u_arg[3], "PTRACE_O_???");
1278                         break;
1279 #endif
1280 #ifdef PTRACE_SETSIGINFO
1281                 case PTRACE_SETSIGINFO: {
1282                         printsiginfo_at(tcp, tcp->u_arg[3]);
1283                         break;
1284                 }
1285 #endif
1286 #ifdef PTRACE_GETSIGINFO
1287                 case PTRACE_GETSIGINFO:
1288                         /* Don't print anything, do it at syscall return. */
1289                         break;
1290 #endif
1291 #ifdef PTRACE_GETREGSET
1292                 case PTRACE_GETREGSET:
1293                         break;
1294                 case PTRACE_SETREGSET:
1295                         tprint_iov(tcp, /*len:*/ 1, tcp->u_arg[3], /*as string:*/ 0);
1296                         break;
1297 #endif
1298                 default:
1299                         tprintf("%#lx", tcp->u_arg[3]);
1300                         break;
1301                 }
1302         } else {
1303                 switch (tcp->u_arg[0]) {
1304                 case PTRACE_PEEKDATA:
1305                 case PTRACE_PEEKTEXT:
1306                 case PTRACE_PEEKUSER:
1307 #ifdef IA64
1308                         return RVAL_HEX;
1309 #else
1310                         printnum(tcp, tcp->u_arg[3], "%#lx");
1311                         break;
1312 #endif
1313 #ifdef PTRACE_GETSIGINFO
1314                 case PTRACE_GETSIGINFO: {
1315                         printsiginfo_at(tcp, tcp->u_arg[3]);
1316                         break;
1317                 }
1318 #endif
1319 #ifdef PTRACE_GETREGSET
1320                 case PTRACE_GETREGSET:
1321                         tprint_iov(tcp, /*len:*/ 1, tcp->u_arg[3], /*as string:*/ 0);
1322                         break;
1323 #endif
1324                 }
1325         }
1326         return 0;
1327 }