1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
15 #include "rom/ets_sys.h"
17 #include "rom/spi_flash.h"
18 #include "sdkconfig.h"
23 extern esp_rom_spiflash_chip_t g_rom_spiflash_chip;
25 esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi)
29 //wait for spi control ready
30 while ((REG_READ(SPI_EXT2_REG(1)) & SPI_ST)) {
32 while ((REG_READ(SPI_EXT2_REG(0)) & SPI_ST)) {
34 //wait for flash status ready
35 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_status(spi, &status)) {
36 return ESP_ROM_SPIFLASH_RESULT_ERR;
38 return ESP_ROM_SPIFLASH_RESULT_OK;
42 /* Modified version of esp_rom_spiflash_unlock() that replaces version in ROM.
44 This works around a bug where esp_rom_spiflash_unlock sometimes reads the wrong
45 high status byte (RDSR2 result) and then copies it back to the
46 flash status, which can cause the CMP bit or Status Register
47 Protect bit to become set.
49 Like other ROM SPI functions, this function is not designed to be
50 called directly from an RTOS environment without taking precautions
51 about interrupts, CPU coordination, flash mapping. However some of
52 the functions in esp_spi_flash.c call it.
54 esp_rom_spiflash_result_t esp_rom_spiflash_unlock()
58 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
60 if (esp_rom_spiflash_read_statushigh(&g_rom_spiflash_chip, &status) != ESP_ROM_SPIFLASH_RESULT_OK) {
61 return ESP_ROM_SPIFLASH_RESULT_ERR;
64 /* Clear all bits except QIE, if it is set.
65 (This is different from ROM esp_rom_spiflash_unlock, which keeps all bits as-is.)
67 status &= ESP_ROM_SPIFLASH_QE;
69 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
70 REG_WRITE(SPI_CMD_REG(SPI_IDX), SPI_FLASH_WREN);
71 while (REG_READ(SPI_CMD_REG(SPI_IDX)) != 0) {
73 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
75 SET_PERI_REG_MASK(SPI_CTRL_REG(SPI_IDX), SPI_WRSR_2B);
76 if (esp_rom_spiflash_write_status(&g_rom_spiflash_chip, status) != ESP_ROM_SPIFLASH_RESULT_OK) {
77 return ESP_ROM_SPIFLASH_RESULT_ERR;
80 return ESP_ROM_SPIFLASH_RESULT_OK;
84 #if CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
86 extern uint8_t g_rom_spiflash_dummy_len_plus[];
89 static esp_rom_spiflash_result_t esp_rom_spiflash_enable_write(esp_rom_spiflash_chip_t *spi);
90 static esp_rom_spiflash_result_t esp_rom_spiflash_enable_qmode(esp_rom_spiflash_chip_t *spi);
91 static esp_rom_spiflash_result_t esp_rom_spiflash_disable_qmode(esp_rom_spiflash_chip_t *spi);
95 static esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip_internal(esp_rom_spiflash_chip_t *spi)
97 esp_rom_spiflash_wait_idle(spi);
100 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_CE);
101 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
103 // check erase is finished.
104 esp_rom_spiflash_wait_idle(spi);
106 return ESP_ROM_SPIFLASH_RESULT_OK;
110 static esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector_internal(esp_rom_spiflash_chip_t *spi, uint32_t addr)
112 //check if addr is 4k alignment
113 if (0 != (addr & 0xfff)) {
114 return ESP_ROM_SPIFLASH_RESULT_ERR;
117 esp_rom_spiflash_wait_idle(spi);
119 // sector erase 4Kbytes erase is sector erase.
120 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff);
121 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_SE);
122 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
124 esp_rom_spiflash_wait_idle(spi);
126 return ESP_ROM_SPIFLASH_RESULT_OK;
130 static esp_rom_spiflash_result_t esp_rom_spiflash_erase_block_internal(esp_rom_spiflash_chip_t *spi, uint32_t addr)
132 esp_rom_spiflash_wait_idle(spi);
134 // sector erase 4Kbytes erase is sector erase.
135 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff);
136 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_BE);
137 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
139 esp_rom_spiflash_wait_idle(spi);
141 return ESP_ROM_SPIFLASH_RESULT_OK;
145 static esp_rom_spiflash_result_t esp_rom_spiflash_program_page_internal(esp_rom_spiflash_chip_t *spi, uint32_t spi_addr,
146 uint32_t *addr_source, int32_t byte_length)
151 uint8_t remain_word_num;
153 //check 4byte alignment
154 if (0 != (byte_length & 0x3)) {
155 return ESP_ROM_SPIFLASH_RESULT_ERR;
158 //check if write in one page
159 if ((spi->page_size) < ((spi_addr % (spi->page_size)) + byte_length)) {
160 return ESP_ROM_SPIFLASH_RESULT_ERR;
163 esp_rom_spiflash_wait_idle(spi);
165 temp_addr = spi_addr;
166 temp_bl = byte_length;
168 while (temp_bl > 0 ) {
169 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(spi)) {
170 return ESP_ROM_SPIFLASH_RESULT_ERR;
172 if ( temp_bl >= ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM ) {
173 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | ( ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM << ESP_ROM_SPIFLASH_BYTES_LEN )); // 32 byte a block
175 for (i = 0; i < (ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM >> 2); i++) {
176 WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++);
178 temp_bl = temp_bl - 32;
179 temp_addr = temp_addr + 32;
181 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | (temp_bl << ESP_ROM_SPIFLASH_BYTES_LEN ));
183 remain_word_num = (0 == (temp_bl & 0x3)) ? (temp_bl >> 2) : (temp_bl >> 2) + 1;
184 for (i = 0; i < remain_word_num; i++) {
185 WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++);
186 temp_bl = temp_bl - 4;
191 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_PP);
192 while ( READ_PERI_REG(PERIPHS_SPI_FLASH_CMD ) != 0 );
194 esp_rom_spiflash_wait_idle(spi);
197 return ESP_ROM_SPIFLASH_RESULT_OK;
201 static esp_rom_spiflash_result_t esp_rom_spiflash_read_data(esp_rom_spiflash_chip_t *spi, uint32_t flash_addr,
202 uint32_t *addr_dest, int32_t byte_length)
207 uint8_t remain_word_num;
209 //address range check
210 if ((flash_addr + byte_length) > (spi->chip_size)) {
211 return ESP_ROM_SPIFLASH_RESULT_ERR;
214 temp_addr = flash_addr;
215 temp_length = byte_length;
217 esp_rom_spiflash_wait_idle(spi);
219 while (temp_length > 0) {
220 if (temp_length >= ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM) {
221 //WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr |(ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << ESP_ROM_SPIFLASH_BYTES_LEN));
222 REG_WRITE(SPI_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_USR_MISO_DBITLEN_S);
223 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8);
224 REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_USR);
225 while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0);
227 for (i = 0; i < (ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM >> 2); i++) {
228 *addr_dest++ = READ_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4);
230 temp_length = temp_length - ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM;
231 temp_addr = temp_addr + ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM;
233 //WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr |(temp_length << ESP_ROM_SPIFLASH_BYTES_LEN ));
234 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8);
235 REG_WRITE(SPI_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_USR_MISO_DBITLEN_S);
236 REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_USR);
237 while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0);
239 remain_word_num = (0 == (temp_length & 0x3)) ? (temp_length >> 2) : (temp_length >> 2) + 1;
240 for (i = 0; i < remain_word_num; i++) {
241 *addr_dest++ = READ_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4);
247 return ESP_ROM_SPIFLASH_RESULT_OK;
250 esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status)
252 uint32_t status_value = ESP_ROM_SPIFLASH_BUSY_FLAG;
254 if (g_rom_spiflash_dummy_len_plus[1] == 0) {
255 while (ESP_ROM_SPIFLASH_BUSY_FLAG == (status_value & ESP_ROM_SPIFLASH_BUSY_FLAG)) {
256 WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, 0); // clear regisrter
257 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_RDSR);
258 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
260 status_value = READ_PERI_REG(PERIPHS_SPI_FLASH_STATUS) & (spi->status_mask);
263 while (ESP_ROM_SPIFLASH_BUSY_FLAG == (status_value & ESP_ROM_SPIFLASH_BUSY_FLAG)) {
264 esp_rom_spiflash_read_user_cmd(&status_value, 0x05);
267 *status = status_value;
269 return ESP_ROM_SPIFLASH_RESULT_OK;
272 esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status)
274 esp_rom_spiflash_result_t ret;
275 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
276 ret = esp_rom_spiflash_read_user_cmd(status, 0x35);
277 *status = *status << 8;
281 esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value)
283 esp_rom_spiflash_wait_idle(spi);
285 // update status value by status_value
286 WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, status_value); // write status regisrter
287 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_WRSR);
288 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
289 esp_rom_spiflash_wait_idle(spi);
291 return ESP_ROM_SPIFLASH_RESULT_OK;
294 static esp_rom_spiflash_result_t esp_rom_spiflash_enable_write(esp_rom_spiflash_chip_t *spi)
296 uint32_t flash_status = 0;
298 esp_rom_spiflash_wait_idle(spi);
301 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_WREN); // enable write operation
302 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
304 // make sure the flash is ready for writing
305 while (ESP_ROM_SPIFLASH_WRENABLE_FLAG != (flash_status & ESP_ROM_SPIFLASH_WRENABLE_FLAG)) {
306 esp_rom_spiflash_read_status(spi, &flash_status);
309 return ESP_ROM_SPIFLASH_RESULT_OK;
312 static esp_rom_spiflash_result_t esp_rom_spiflash_enable_qmode(esp_rom_spiflash_chip_t *spi)
314 uint32_t flash_status;
316 //read QE bit, not write if QE
317 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_statushigh(spi, &status)) {
318 return ESP_ROM_SPIFLASH_RESULT_ERR;
320 if (status & ESP_ROM_SPIFLASH_QE) {
321 return ESP_ROM_SPIFLASH_RESULT_OK;
324 //enable 2 byte status writing
325 SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN);
327 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(spi)) {
328 return ESP_ROM_SPIFLASH_RESULT_ERR;
331 esp_rom_spiflash_read_status(spi, &flash_status);
333 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_write_status(spi, flash_status | ESP_ROM_SPIFLASH_QE)) {
334 return ESP_ROM_SPIFLASH_RESULT_ERR;
337 return ESP_ROM_SPIFLASH_RESULT_OK;
340 static esp_rom_spiflash_result_t esp_rom_spiflash_disable_qmode(esp_rom_spiflash_chip_t *spi)
342 uint32_t flash_status;
345 //read QE bit, not write if not QE
346 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_statushigh(spi, &status)) {
347 return ESP_ROM_SPIFLASH_RESULT_ERR;
349 //ets_printf("status %08x, line:%u\n", status, __LINE__);
351 if (!(status & ESP_ROM_SPIFLASH_QE)) {
352 return ESP_ROM_SPIFLASH_RESULT_OK;
355 //enable 2 byte status writing
356 SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN);
358 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(spi)) {
359 return ESP_ROM_SPIFLASH_RESULT_ERR;
362 esp_rom_spiflash_read_status(spi, &flash_status);
364 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_write_status(spi, flash_status & 0xff)) {
365 return ESP_ROM_SPIFLASH_RESULT_ERR;
368 return ESP_ROM_SPIFLASH_RESULT_OK;
371 static void spi_cache_mode_switch(uint32_t modebit)
373 if ((modebit & SPI_FREAD_QIO) && (modebit & SPI_FASTRD_MODE)) {
374 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI);
375 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
376 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_QIO_ADDR_BITSLEN);
377 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_QIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
378 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0xEB);
379 } else if (modebit & SPI_FASTRD_MODE) {
380 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI);
381 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
382 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_FAST_ADDR_BITSLEN);
383 if ((modebit & SPI_FREAD_QUAD)) {
384 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x6B);
385 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
386 } else if ((modebit & SPI_FREAD_DIO)) {
387 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_DIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
388 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0xBB);
389 } else if ((modebit & SPI_FREAD_DUAL)) {
390 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
391 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x3B);
393 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
394 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x0B);
397 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI);
398 if (g_rom_spiflash_dummy_len_plus[0] == 0) {
399 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_DUMMY);
401 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_DUMMY);
402 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[0] - 1);
404 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_ADDR);
405 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_SIO_ADDR_BITSLEN);
406 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x03);
411 esp_rom_spiflash_result_t esp_rom_spiflash_lock()
415 //read QE bit, not write if not QE
416 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_statushigh(&g_rom_spiflash_chip, &status)) {
417 return ESP_ROM_SPIFLASH_RESULT_ERR;
419 //enable 2 byte status writing
420 SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN);
422 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
423 return ESP_ROM_SPIFLASH_RESULT_ERR;
426 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_write_status(&g_rom_spiflash_chip, status | ESP_ROM_SPIFLASH_WR_PROTECT)) {
427 return ESP_ROM_SPIFLASH_RESULT_ERR;
430 return ESP_ROM_SPIFLASH_RESULT_OK;
434 esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode, bool legacy)
438 while ((REG_READ(SPI_EXT2_REG(1)) & SPI_ST)) {
440 while ((REG_READ(SPI_EXT2_REG(0)) & SPI_ST)) {
443 CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_FREAD_QIO | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_DUAL | SPI_FASTRD_MODE);
444 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(0), SPI_FREAD_QIO | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_DUAL | SPI_FASTRD_MODE);
445 //configure read mode
447 case ESP_ROM_SPIFLASH_QIO_MODE : modebit = SPI_FREAD_QIO | SPI_FASTRD_MODE; break;
448 case ESP_ROM_SPIFLASH_QOUT_MODE : modebit = SPI_FREAD_QUAD | SPI_FASTRD_MODE; break;
449 case ESP_ROM_SPIFLASH_DIO_MODE : modebit = SPI_FREAD_DIO | SPI_FASTRD_MODE; break;
450 case ESP_ROM_SPIFLASH_DOUT_MODE : modebit = SPI_FREAD_DUAL | SPI_FASTRD_MODE; break;
451 case ESP_ROM_SPIFLASH_FASTRD_MODE: modebit = SPI_FASTRD_MODE; break;
452 case ESP_ROM_SPIFLASH_SLOWRD_MODE: modebit = 0; break;
453 default : modebit = 0;
456 if ((ESP_ROM_SPIFLASH_QIO_MODE == mode) || (ESP_ROM_SPIFLASH_QOUT_MODE == mode)) {
457 esp_rom_spiflash_enable_qmode(&g_rom_spiflash_chip);
459 //do not need disable QMode in faster boot
461 esp_rom_spiflash_disable_qmode(&g_rom_spiflash_chip);
465 SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, modebit);
466 SET_PERI_REG_MASK(SPI_CTRL_REG(0), modebit);
467 spi_cache_mode_switch(modebit);
469 return ESP_ROM_SPIFLASH_RESULT_OK;
472 esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip()
474 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
475 return ESP_ROM_SPIFLASH_RESULT_ERR;
478 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_chip_internal(&g_rom_spiflash_chip)) {
479 return ESP_ROM_SPIFLASH_RESULT_ERR;
482 return ESP_ROM_SPIFLASH_RESULT_OK;
485 esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num)
487 // flash write is always 1 line currently
488 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
489 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
492 if (block_num >= ((g_rom_spiflash_chip.chip_size) / (g_rom_spiflash_chip.block_size))) {
493 return ESP_ROM_SPIFLASH_RESULT_ERR;
496 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
497 return ESP_ROM_SPIFLASH_RESULT_ERR;
500 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_block_internal(&g_rom_spiflash_chip, block_num * (g_rom_spiflash_chip.block_size))) {
501 return ESP_ROM_SPIFLASH_RESULT_ERR;
503 return ESP_ROM_SPIFLASH_RESULT_OK;
506 esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num)
508 // flash write is always 1 line currently
509 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
510 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
513 if (sector_num >= ((g_rom_spiflash_chip.chip_size) / (g_rom_spiflash_chip.sector_size))) {
514 return ESP_ROM_SPIFLASH_RESULT_ERR;
517 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
518 return ESP_ROM_SPIFLASH_RESULT_ERR;
521 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_sector_internal(&g_rom_spiflash_chip, sector_num * (g_rom_spiflash_chip.sector_size))) {
522 return ESP_ROM_SPIFLASH_RESULT_ERR;
525 return ESP_ROM_SPIFLASH_RESULT_OK;
528 esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t target, const uint32_t *src_addr, int32_t len)
531 uint32_t pgm_len, pgm_num;
534 // flash write is always 1 line currently
535 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
536 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
539 if ( (target + len) > (g_rom_spiflash_chip.chip_size)) {
540 return ESP_ROM_SPIFLASH_RESULT_ERR;
543 page_size = g_rom_spiflash_chip.page_size;
544 pgm_len = page_size - (target % page_size);
546 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
547 target, (uint32_t *)src_addr, len)) {
548 return ESP_ROM_SPIFLASH_RESULT_ERR;
551 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
552 target, (uint32_t *)src_addr, pgm_len)) {
553 return ESP_ROM_SPIFLASH_RESULT_ERR;
557 pgm_num = (len - pgm_len) / page_size;
558 for (i = 0; i < pgm_num; i++) {
559 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
560 target + pgm_len, (uint32_t *)src_addr + (pgm_len >> 2), page_size)) {
561 return ESP_ROM_SPIFLASH_RESULT_ERR;
563 pgm_len += page_size;
566 //remain parts to program
567 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
568 target + pgm_len, (uint32_t *)src_addr + (pgm_len >> 2), len - pgm_len)) {
569 return ESP_ROM_SPIFLASH_RESULT_ERR;
572 return ESP_ROM_SPIFLASH_RESULT_OK;
575 esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len)
577 esp_rom_spiflash_result_t ret = ESP_ROM_SPIFLASH_RESULT_OK;
580 if ((flash_addr & 0x1f) || (len & 0x1f)) { //check 32 byte alignment
581 return ESP_ROM_SPIFLASH_RESULT_ERR;
584 esp_rom_spiflash_write_encrypted_enable();
586 for (i = 0; i < (len >> 5); i++) {
587 if ((ret = esp_rom_spiflash_prepare_encrypted_data(flash_addr + (i << 5), data + (i << 3))) != ESP_ROM_SPIFLASH_RESULT_OK) {
591 if ((ret = esp_rom_spiflash_write(flash_addr + (i << 5), data, 32)) != ESP_ROM_SPIFLASH_RESULT_OK) {
596 esp_rom_spiflash_write_encrypted_disable();
602 esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t target, uint32_t *dest_addr, int32_t len)
604 // QIO or SIO, non-QIO regard as SIO
606 modebit = READ_PERI_REG(PERIPHS_SPI_FLASH_CTRL);
607 if ((modebit & SPI_FREAD_QIO) && (modebit & SPI_FASTRD_MODE)) {
608 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI);
609 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
610 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_QIO_ADDR_BITSLEN);
611 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, SPI1_R_QIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[1]);
612 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0xEB);
613 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0xEB);
614 } else if (modebit & SPI_FASTRD_MODE) {
615 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI);
616 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR);
617 if (modebit & SPI_FREAD_DIO) {
618 if (g_rom_spiflash_dummy_len_plus[1] == 0) {
619 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
620 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_DIO_ADDR_BITSLEN);
621 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0xBB);
623 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
624 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_DIO_ADDR_BITSLEN);
625 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[1] - 1);
626 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0xBB);
629 if ((modebit & SPI_FREAD_QUAD)) {
630 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x6B);
631 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x6B);
632 } else if ((modebit & SPI_FREAD_DUAL)) {
633 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x3B);
634 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x3B);
636 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x0B);
637 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x0B);
639 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
640 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_FAST_ADDR_BITSLEN);
641 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, SPI1_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[1]);
644 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI);
645 if (g_rom_spiflash_dummy_len_plus[1] == 0) {
646 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
648 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
649 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[1] - 1);
651 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR);
652 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_SIO_ADDR_BITSLEN);
653 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x03);
654 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x03);
657 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_data(&g_rom_spiflash_chip, target, dest_addr, len)) {
658 return ESP_ROM_SPIFLASH_RESULT_ERR;
660 return ESP_ROM_SPIFLASH_RESULT_OK;
663 esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len)
665 int32_t total_sector_num;
666 int32_t head_sector_num;
668 uint32_t sector_num_per_block;
670 //set read mode to Fastmode ,not QDIO mode for erase
671 esp_rom_spiflash_config_readmode(ESP_ROM_SPIFLASH_SLOWRD_MODE, true);
673 //check if area is oversize of flash
674 if ((start_addr + area_len) > g_rom_spiflash_chip.chip_size) {
675 return ESP_ROM_SPIFLASH_RESULT_ERR;
678 //start_addr is aligned as sector boundary
679 if (0 != (start_addr % g_rom_spiflash_chip.sector_size)) {
680 return ESP_ROM_SPIFLASH_RESULT_ERR;
683 //Unlock flash to enable erase
684 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_unlock(/*&g_rom_spiflash_chip*/)) {
685 return ESP_ROM_SPIFLASH_RESULT_ERR;
688 sector_no = start_addr / g_rom_spiflash_chip.sector_size;
689 sector_num_per_block = g_rom_spiflash_chip.block_size / g_rom_spiflash_chip.sector_size;
690 total_sector_num = (0 == (area_len % g_rom_spiflash_chip.sector_size)) ? area_len / g_rom_spiflash_chip.sector_size :
691 1 + (area_len / g_rom_spiflash_chip.sector_size);
693 //check if erase area reach over block boundary
694 head_sector_num = sector_num_per_block - (sector_no % sector_num_per_block);
696 head_sector_num = (head_sector_num >= total_sector_num) ? total_sector_num : head_sector_num;
698 //JJJ, BUG of 6.0 erase
699 //middle part of area is aligned by blocks
700 total_sector_num -= head_sector_num;
702 //head part of area is erased
703 while (0 != head_sector_num) {
704 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_sector(sector_no)) {
705 return ESP_ROM_SPIFLASH_RESULT_ERR;
710 while (total_sector_num > sector_num_per_block) {
711 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_block(sector_no / sector_num_per_block)) {
712 return ESP_ROM_SPIFLASH_RESULT_ERR;
714 sector_no += sector_num_per_block;
715 total_sector_num -= sector_num_per_block;
718 //tail part of area burn
719 while (0 < total_sector_num) {
720 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_sector(sector_no)) {
721 return ESP_ROM_SPIFLASH_RESULT_ERR;
727 return ESP_ROM_SPIFLASH_RESULT_OK;