1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
20 #include <freertos/FreeRTOS.h>
21 #include <freertos/task.h>
22 #include <freertos/semphr.h>
23 #include <rom/spi_flash.h>
24 #include <rom/cache.h>
26 #include <soc/dport_reg.h>
27 #include "sdkconfig.h"
30 #include "esp_spi_flash.h"
31 #include "esp_flash_encrypt.h"
33 #include "cache_utils.h"
36 // Enable built-in checks in queue.h in debug builds
39 #include "rom/queue.h"
41 #define REGIONS_COUNT 4
42 #define PAGES_PER_REGION 64
43 #define INVALID_ENTRY_VAL 0x100
44 #define VADDR0_START_ADDR 0x3F400000
45 #define VADDR1_START_ADDR 0x40000000
46 #define VADDR1_FIRST_USABLE_ADDR 0x400D0000
47 #define PRO_IRAM0_FIRST_USABLE_PAGE ((VADDR1_FIRST_USABLE_ADDR - VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + 64)
49 /* Ensure pages in a region haven't been marked as written via
50 spi_flash_mark_modified_region(). If the page has
51 been written, flush the entire flash cache before returning.
53 This ensures stale cache entries are never read after fresh calls
54 to spi_flash_mmap(), while keeping the number of cache flushes to a
57 Returns true if cache was flushed.
59 static bool spi_flash_ensure_unmodified_region(size_t start_addr, size_t length);
61 typedef struct mmap_entry_{
65 LIST_ENTRY(mmap_entry_) entries;
69 static LIST_HEAD(mmap_entries_head, mmap_entry_) s_mmap_entries_head =
70 LIST_HEAD_INITIALIZER(s_mmap_entries_head);
71 static uint8_t s_mmap_page_refcnt[REGIONS_COUNT * PAGES_PER_REGION] = {0};
72 static uint32_t s_mmap_last_handle = 0;
75 static void IRAM_ATTR spi_flash_mmap_init()
77 for (int i = 0; i < REGIONS_COUNT * PAGES_PER_REGION; ++i) {
78 uint32_t entry_pro = DPORT_PRO_FLASH_MMU_TABLE[i];
79 uint32_t entry_app = DPORT_APP_FLASH_MMU_TABLE[i];
80 if (entry_pro != entry_app) {
81 // clean up entries used by boot loader
83 DPORT_PRO_FLASH_MMU_TABLE[i] = 0;
85 if ((entry_pro & 0x100) == 0 && (i == 0 || i == PRO_IRAM0_FIRST_USABLE_PAGE || entry_pro != 0)) {
86 s_mmap_page_refcnt[i] = 1;
91 esp_err_t IRAM_ATTR spi_flash_mmap(size_t src_addr, size_t size, spi_flash_mmap_memory_t memory,
92 const void** out_ptr, spi_flash_mmap_handle_t* out_handle)
95 bool did_flush, need_flush = false;
96 mmap_entry_t* new_entry = (mmap_entry_t*) malloc(sizeof(mmap_entry_t));
98 return ESP_ERR_NO_MEM;
100 if (src_addr & 0xffff) {
101 return ESP_ERR_INVALID_ARG;
103 if (src_addr + size > g_rom_flashchip.chip_size) {
104 return ESP_ERR_INVALID_ARG;
107 spi_flash_disable_interrupts_caches_and_other_cpu();
109 did_flush = spi_flash_ensure_unmodified_region(src_addr, size);
111 if (s_mmap_page_refcnt[0] == 0) {
112 spi_flash_mmap_init();
114 // figure out the memory region where we should look for pages
115 int region_begin; // first page to check
116 int region_size; // number of pages to check
117 uint32_t region_addr; // base address of memory region
118 if (memory == SPI_FLASH_MMAP_DATA) {
122 region_addr = VADDR0_START_ADDR;
124 // only part of VAddr1 is usable, so adjust for that
125 region_begin = VADDR1_FIRST_USABLE_ADDR;
126 region_size = 3 * 64 - region_begin;
127 region_addr = VADDR1_FIRST_USABLE_ADDR;
129 // region which should be mapped
130 int phys_page = src_addr / SPI_FLASH_MMU_PAGE_SIZE;
131 int page_count = (size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE;
132 // The following part searches for a range of MMU entries which can be used.
133 // Algorithm is essentially naïve strstr algorithm, except that unused MMU
134 // entries are treated as wildcards.
136 int end = region_begin + region_size - page_count;
137 for (start = region_begin; start < end; ++start) {
138 int page = phys_page;
140 for (pos = start; pos < start + page_count; ++pos, ++page) {
141 int table_val = (int) DPORT_PRO_FLASH_MMU_TABLE[pos];
142 uint8_t refcnt = s_mmap_page_refcnt[pos];
143 if (refcnt != 0 && table_val != page) {
147 // whole mapping range matched, bail out
148 if (pos - start == page_count) {
152 // checked all the region(s) and haven't found anything?
156 ret = ESP_ERR_NO_MEM;
158 // set up mapping using pages [start, start + page_count)
159 uint32_t entry_val = (uint32_t) phys_page;
160 for (int i = start; i != start + page_count; ++i, ++entry_val) {
161 // sanity check: we won't reconfigure entries with non-zero reference count
162 assert(s_mmap_page_refcnt[i] == 0 ||
163 (DPORT_PRO_FLASH_MMU_TABLE[i] == entry_val &&
164 DPORT_APP_FLASH_MMU_TABLE[i] == entry_val));
165 if (s_mmap_page_refcnt[i] == 0) {
166 if (DPORT_PRO_FLASH_MMU_TABLE[i] != entry_val || DPORT_APP_FLASH_MMU_TABLE[i] != entry_val) {
167 DPORT_PRO_FLASH_MMU_TABLE[i] = entry_val;
168 DPORT_APP_FLASH_MMU_TABLE[i] = entry_val;
172 ++s_mmap_page_refcnt[i];
175 LIST_INSERT_HEAD(&s_mmap_entries_head, new_entry, entries);
176 new_entry->page = start;
177 new_entry->count = page_count;
178 new_entry->handle = ++s_mmap_last_handle;
179 *out_handle = new_entry->handle;
180 *out_ptr = (void*) (region_addr + start * SPI_FLASH_MMU_PAGE_SIZE);
184 /* This is a temporary fix for an issue where some
185 encrypted cache reads may see stale data.
187 Working on a long term fix that doesn't require invalidating
190 if (esp_flash_encryption_enabled() && !did_flush && need_flush) {
195 spi_flash_enable_interrupts_caches_and_other_cpu();
196 if (*out_ptr == NULL) {
202 void IRAM_ATTR spi_flash_munmap(spi_flash_mmap_handle_t handle)
204 spi_flash_disable_interrupts_caches_and_other_cpu();
206 // look for handle in linked list
207 for (it = LIST_FIRST(&s_mmap_entries_head); it != NULL; it = LIST_NEXT(it, entries)) {
208 if (it->handle == handle) {
209 // for each page, decrement reference counter
210 // if reference count is zero, disable MMU table entry to
211 // facilitate debugging of use-after-free conditions
212 for (int i = it->page; i < it->page + it->count; ++i) {
213 assert(s_mmap_page_refcnt[i] > 0);
214 if (--s_mmap_page_refcnt[i] == 0) {
215 DPORT_PRO_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL;
216 DPORT_APP_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL;
219 LIST_REMOVE(it, entries);
223 spi_flash_enable_interrupts_caches_and_other_cpu();
225 assert(0 && "invalid handle, or handle already unmapped");
230 void spi_flash_mmap_dump()
232 if (s_mmap_page_refcnt[0] == 0) {
233 spi_flash_mmap_init();
236 for (it = LIST_FIRST(&s_mmap_entries_head); it != NULL; it = LIST_NEXT(it, entries)) {
237 printf("handle=%d page=%d count=%d\n", it->handle, it->page, it->count);
239 for (int i = 0; i < REGIONS_COUNT * PAGES_PER_REGION; ++i) {
240 if (s_mmap_page_refcnt[i] != 0) {
241 printf("page %d: refcnt=%d paddr=%d\n",
242 i, (int) s_mmap_page_refcnt[i], DPORT_PRO_FLASH_MMU_TABLE[i]);
247 /* 256-bit (up to 16MB of 64KB pages) bitset of all flash pages
248 that have been written to since last cache flush.
250 Before mmaping a page, need to flush caches if that page has been
253 Note: It's possible to do some additional performance tweaks to
254 this algorithm, as we actually only need to flush caches if a page
255 was first mmapped, then written to, then is about to be mmaped a
256 second time. This is a fair bit more complex though, so unless
257 there's an access pattern that this would significantly boost then
258 it's probably not worth it.
260 static uint32_t written_pages[256/32];
262 static bool update_written_pages(size_t start_addr, size_t length, bool mark);
264 void IRAM_ATTR spi_flash_mark_modified_region(size_t start_addr, size_t length)
266 update_written_pages(start_addr, length, true);
269 static IRAM_ATTR bool spi_flash_ensure_unmodified_region(size_t start_addr, size_t length)
271 return update_written_pages(start_addr, length, false);
274 /* generic implementation for the previous two functions */
275 static inline IRAM_ATTR bool update_written_pages(size_t start_addr, size_t length, bool mark)
277 /* align start_addr & length to full MMU pages */
278 uint32_t page_start_addr = start_addr & ~(SPI_FLASH_MMU_PAGE_SIZE-1);
279 length += (start_addr - page_start_addr);
280 length = (length + SPI_FLASH_MMU_PAGE_SIZE - 1) & ~(SPI_FLASH_MMU_PAGE_SIZE-1);
281 for (uint32_t addr = page_start_addr; addr < page_start_addr + length; addr += SPI_FLASH_MMU_PAGE_SIZE) {
282 int page = addr / SPI_FLASH_MMU_PAGE_SIZE;
284 return false; /* invalid address */
288 uint32_t bit = 1 << (page % 32);
291 written_pages[idx] |= bit;
292 } else if (written_pages[idx] & bit) {
293 /* it is tempting to write a version of this that only
294 flushes each CPU's cache as needed. However this is
295 tricky because mmaped memory can be used on un-pinned
296 cores, or the pointer passed between CPUs.
299 #ifndef CONFIG_FREERTOS_UNICORE
302 bzero(written_pages, sizeof(written_pages));