1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
20 #include <freertos/FreeRTOS.h>
21 #include <freertos/task.h>
22 #include <freertos/semphr.h>
23 #include <rom/spi_flash.h>
24 #include <rom/cache.h>
26 #include <soc/dport_reg.h>
27 #include "sdkconfig.h"
30 #include "esp_spi_flash.h"
31 #include "esp_flash_encrypt.h"
33 #include "cache_utils.h"
36 // Enable built-in checks in queue.h in debug builds
39 #include "rom/queue.h"
41 #define REGIONS_COUNT 4
42 #define PAGES_PER_REGION 64
43 #define INVALID_ENTRY_VAL 0x100
44 #define VADDR0_START_ADDR 0x3F400000
45 #define VADDR1_START_ADDR 0x40000000
46 #define VADDR1_FIRST_USABLE_ADDR 0x400D0000
47 #define PRO_IRAM0_FIRST_USABLE_PAGE ((VADDR1_FIRST_USABLE_ADDR - VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + 64)
49 /* Ensure pages in a region haven't been marked as written via
50 spi_flash_mark_modified_region(). If the page has
51 been written, flush the entire flash cache before returning.
53 This ensures stale cache entries are never read after fresh calls
54 to spi_flash_mmap(), while keeping the number of cache flushes to a
57 Returns true if cache was flushed.
59 static bool spi_flash_ensure_unmodified_region(size_t start_addr, size_t length);
61 typedef struct mmap_entry_{
65 LIST_ENTRY(mmap_entry_) entries;
69 static LIST_HEAD(mmap_entries_head, mmap_entry_) s_mmap_entries_head =
70 LIST_HEAD_INITIALIZER(s_mmap_entries_head);
71 static uint8_t s_mmap_page_refcnt[REGIONS_COUNT * PAGES_PER_REGION] = {0};
72 static uint32_t s_mmap_last_handle = 0;
75 static void IRAM_ATTR spi_flash_mmap_init()
77 if (s_mmap_page_refcnt[0] != 0) {
78 return; /* mmap data already initialised */
81 for (int i = 0; i < REGIONS_COUNT * PAGES_PER_REGION; ++i) {
82 uint32_t entry_pro = DPORT_PRO_FLASH_MMU_TABLE[i];
83 uint32_t entry_app = DPORT_APP_FLASH_MMU_TABLE[i];
84 if (entry_pro != entry_app) {
85 // clean up entries used by boot loader
86 entry_pro = INVALID_ENTRY_VAL;
87 DPORT_PRO_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL;
89 if ((entry_pro & INVALID_ENTRY_VAL) == 0 && (i == 0 || i == PRO_IRAM0_FIRST_USABLE_PAGE || entry_pro != 0)) {
90 s_mmap_page_refcnt[i] = 1;
92 DPORT_PRO_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL;
93 DPORT_APP_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL;
98 esp_err_t IRAM_ATTR spi_flash_mmap(size_t src_addr, size_t size, spi_flash_mmap_memory_t memory,
99 const void** out_ptr, spi_flash_mmap_handle_t* out_handle)
102 bool did_flush, need_flush = false;
103 if (src_addr & 0xffff) {
104 return ESP_ERR_INVALID_ARG;
106 if (src_addr + size > g_rom_flashchip.chip_size) {
107 return ESP_ERR_INVALID_ARG;
109 mmap_entry_t* new_entry = (mmap_entry_t*) malloc(sizeof(mmap_entry_t));
110 if (new_entry == 0) {
111 return ESP_ERR_NO_MEM;
114 spi_flash_disable_interrupts_caches_and_other_cpu();
116 did_flush = spi_flash_ensure_unmodified_region(src_addr, size);
118 spi_flash_mmap_init();
119 // figure out the memory region where we should look for pages
120 int region_begin; // first page to check
121 int region_size; // number of pages to check
122 uint32_t region_addr; // base address of memory region
123 if (memory == SPI_FLASH_MMAP_DATA) {
127 region_addr = VADDR0_START_ADDR;
129 // only part of VAddr1 is usable, so adjust for that
130 region_begin = PRO_IRAM0_FIRST_USABLE_PAGE;
131 region_size = 3 * 64 - region_begin;
132 region_addr = VADDR1_FIRST_USABLE_ADDR;
134 // region which should be mapped
135 int phys_page = src_addr / SPI_FLASH_MMU_PAGE_SIZE;
136 int page_count = (size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE;
137 // The following part searches for a range of MMU entries which can be used.
138 // Algorithm is essentially naïve strstr algorithm, except that unused MMU
139 // entries are treated as wildcards.
141 int end = region_begin + region_size - page_count;
142 for (start = region_begin; start < end; ++start) {
143 int page = phys_page;
145 for (pos = start; pos < start + page_count; ++pos, ++page) {
146 int table_val = (int) DPORT_PRO_FLASH_MMU_TABLE[pos];
147 uint8_t refcnt = s_mmap_page_refcnt[pos];
148 if (refcnt != 0 && table_val != page) {
152 // whole mapping range matched, bail out
153 if (pos - start == page_count) {
157 // checked all the region(s) and haven't found anything?
161 ret = ESP_ERR_NO_MEM;
163 // set up mapping using pages [start, start + page_count)
164 uint32_t entry_val = (uint32_t) phys_page;
165 for (int i = start; i != start + page_count; ++i, ++entry_val) {
166 // sanity check: we won't reconfigure entries with non-zero reference count
167 assert(s_mmap_page_refcnt[i] == 0 ||
168 (DPORT_PRO_FLASH_MMU_TABLE[i] == entry_val &&
169 DPORT_APP_FLASH_MMU_TABLE[i] == entry_val));
170 if (s_mmap_page_refcnt[i] == 0) {
171 if (DPORT_PRO_FLASH_MMU_TABLE[i] != entry_val || DPORT_APP_FLASH_MMU_TABLE[i] != entry_val) {
172 DPORT_PRO_FLASH_MMU_TABLE[i] = entry_val;
173 DPORT_APP_FLASH_MMU_TABLE[i] = entry_val;
177 ++s_mmap_page_refcnt[i];
180 LIST_INSERT_HEAD(&s_mmap_entries_head, new_entry, entries);
181 new_entry->page = start;
182 new_entry->count = page_count;
183 new_entry->handle = ++s_mmap_last_handle;
184 *out_handle = new_entry->handle;
185 *out_ptr = (void*) (region_addr + (start - region_begin) * SPI_FLASH_MMU_PAGE_SIZE);
189 /* This is a temporary fix for an issue where some
190 cache reads may see stale data.
192 Working on a long term fix that doesn't require invalidating
195 if (!did_flush && need_flush) {
200 spi_flash_enable_interrupts_caches_and_other_cpu();
201 if (*out_ptr == NULL) {
207 void IRAM_ATTR spi_flash_munmap(spi_flash_mmap_handle_t handle)
209 spi_flash_disable_interrupts_caches_and_other_cpu();
211 // look for handle in linked list
212 for (it = LIST_FIRST(&s_mmap_entries_head); it != NULL; it = LIST_NEXT(it, entries)) {
213 if (it->handle == handle) {
214 // for each page, decrement reference counter
215 // if reference count is zero, disable MMU table entry to
216 // facilitate debugging of use-after-free conditions
217 for (int i = it->page; i < it->page + it->count; ++i) {
218 assert(s_mmap_page_refcnt[i] > 0);
219 if (--s_mmap_page_refcnt[i] == 0) {
220 DPORT_PRO_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL;
221 DPORT_APP_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL;
224 LIST_REMOVE(it, entries);
228 spi_flash_enable_interrupts_caches_and_other_cpu();
230 assert(0 && "invalid handle, or handle already unmapped");
235 void spi_flash_mmap_dump()
237 spi_flash_mmap_init();
239 for (it = LIST_FIRST(&s_mmap_entries_head); it != NULL; it = LIST_NEXT(it, entries)) {
240 printf("handle=%d page=%d count=%d\n", it->handle, it->page, it->count);
242 for (int i = 0; i < REGIONS_COUNT * PAGES_PER_REGION; ++i) {
243 if (s_mmap_page_refcnt[i] != 0) {
244 printf("page %d: refcnt=%d paddr=%d\n",
245 i, (int) s_mmap_page_refcnt[i], DPORT_PRO_FLASH_MMU_TABLE[i]);
250 /* 256-bit (up to 16MB of 64KB pages) bitset of all flash pages
251 that have been written to since last cache flush.
253 Before mmaping a page, need to flush caches if that page has been
256 Note: It's possible to do some additional performance tweaks to
257 this algorithm, as we actually only need to flush caches if a page
258 was first mmapped, then written to, then is about to be mmaped a
259 second time. This is a fair bit more complex though, so unless
260 there's an access pattern that this would significantly boost then
261 it's probably not worth it.
263 static uint32_t written_pages[256/32];
265 static bool update_written_pages(size_t start_addr, size_t length, bool mark);
267 void IRAM_ATTR spi_flash_mark_modified_region(size_t start_addr, size_t length)
269 update_written_pages(start_addr, length, true);
272 static IRAM_ATTR bool spi_flash_ensure_unmodified_region(size_t start_addr, size_t length)
274 return update_written_pages(start_addr, length, false);
277 /* generic implementation for the previous two functions */
278 static inline IRAM_ATTR bool update_written_pages(size_t start_addr, size_t length, bool mark)
280 /* align start_addr & length to full MMU pages */
281 uint32_t page_start_addr = start_addr & ~(SPI_FLASH_MMU_PAGE_SIZE-1);
282 length += (start_addr - page_start_addr);
283 length = (length + SPI_FLASH_MMU_PAGE_SIZE - 1) & ~(SPI_FLASH_MMU_PAGE_SIZE-1);
284 for (uint32_t addr = page_start_addr; addr < page_start_addr + length; addr += SPI_FLASH_MMU_PAGE_SIZE) {
285 int page = addr / SPI_FLASH_MMU_PAGE_SIZE;
287 return false; /* invalid address */
291 uint32_t bit = 1 << (page % 32);
294 written_pages[idx] |= bit;
295 } else if (written_pages[idx] & bit) {
296 /* it is tempting to write a version of this that only
297 flushes each CPU's cache as needed. However this is
298 tricky because mmaped memory can be used on un-pinned
299 cores, or the pointer passed between CPUs.
302 #ifndef CONFIG_FREERTOS_UNICORE
305 bzero(written_pages, sizeof(written_pages));
313 uint32_t spi_flash_cache2phys(const void *cached)
315 intptr_t c = (intptr_t)cached;
317 if (c >= VADDR1_START_ADDR && c < VADDR1_FIRST_USABLE_ADDR) {
318 /* IRAM address, doesn't map to flash */
319 return SPI_FLASH_CACHE2PHYS_FAIL;
321 else if (c < VADDR1_FIRST_USABLE_ADDR) {
322 /* expect cache is in DROM */
323 cache_page = (c - VADDR0_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE;
325 /* expect cache is in IROM */
326 cache_page = (c - VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + 64;
329 if (cache_page >= 256) {
330 /* cached address was not in IROM or DROM */
331 return SPI_FLASH_CACHE2PHYS_FAIL;
333 uint32_t phys_page = DPORT_PRO_FLASH_MMU_TABLE[cache_page];
334 if (phys_page == INVALID_ENTRY_VAL) {
335 /* page is not mapped */
336 return SPI_FLASH_CACHE2PHYS_FAIL;
338 uint32_t phys_offs = phys_page * SPI_FLASH_MMU_PAGE_SIZE;
339 return phys_offs | (c & (SPI_FLASH_MMU_PAGE_SIZE-1));
343 const void *spi_flash_phys2cache(uint32_t phys_offs, spi_flash_mmap_memory_t memory)
345 uint32_t phys_page = phys_offs / SPI_FLASH_MMU_PAGE_SIZE;
346 int start, end, page_delta;
349 if (memory == SPI_FLASH_MMAP_DATA) {
352 base = VADDR0_START_ADDR;
355 start = PRO_IRAM0_FIRST_USABLE_PAGE;
357 base = VADDR1_START_ADDR;
361 for (int i = start; i < end; i++) {
362 if (DPORT_PRO_FLASH_MMU_TABLE[i] == phys_page) {
364 intptr_t cache_page = base + (SPI_FLASH_MMU_PAGE_SIZE * i);
365 return (const void *) (cache_page | (phys_offs & (SPI_FLASH_MMU_PAGE_SIZE-1)));