1 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
19 #include "rom/ets_sys.h"
23 #include "soc/rtc_cntl_reg.h"
24 #include "soc/rtc_io_reg.h"
25 #include "soc/sens_reg.h"
26 #include "soc/dport_reg.h"
27 #include "soc/efuse_reg.h"
28 #include "soc/apb_ctrl_reg.h"
29 #include "i2c_rtc_clk.h"
31 #include "sdkconfig.h"
35 /* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting */
36 #define RTC_FAST_CLK_FREQ_8M 8500000
37 #define RTC_SLOW_CLK_FREQ_150K 150000
38 #define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256)
39 #define RTC_SLOW_CLK_FREQ_32K 32768
41 static const char* TAG = "rtc_clk";
43 /* Various constants related to the analog internals of the chip.
44 * Defined here because they don't have any use outside of this file.
47 #define BBPLL_ENDIV5_VAL_320M 0x43
48 #define BBPLL_BBADC_DSMP_VAL_320M 0x84
49 #define BBPLL_ENDIV5_VAL_480M 0xc3
50 #define BBPLL_BBADC_DSMP_VAL_480M 0x74
52 #define APLL_SDM_STOP_VAL_1 0x09
53 #define APLL_SDM_STOP_VAL_2_REV0 0x69
54 #define APLL_SDM_STOP_VAL_2_REV1 0x49
56 #define APLL_CAL_DELAY_1 0x0f
57 #define APLL_CAL_DELAY_2 0x3f
58 #define APLL_CAL_DELAY_3 0x1f
60 #define XTAL_32K_DAC_VAL 1
61 #define XTAL_32K_DRES_VAL 3
62 #define XTAL_32K_DBIAS_VAL 0
64 #define XTAL_32K_BOOTSTRAP_DAC_VAL 3
65 #define XTAL_32K_BOOTSTRAP_DRES_VAL 3
66 #define XTAL_32K_BOOTSTRAP_DBIAS_VAL 0
67 #define XTAL_32K_BOOTSTRAP_TIME_US 7
69 /* Delays for various clock sources to be enabled/switched.
70 * All values are in microseconds.
71 * TODO: some of these are excessive, and should be reduced.
73 #define DELAY_CPU_FREQ_SWITCH_TO_XTAL_WITH_150K 80
74 #define DELAY_CPU_FREQ_SWITCH_TO_XTAL_WITH_32K 160
75 #define DELAY_CPU_FREQ_SWITCH_TO_PLL 10
76 #define DELAY_PLL_DBIAS_RAISE 3
77 #define DELAY_PLL_ENABLE_WITH_150K 80
78 #define DELAY_PLL_ENABLE_WITH_32K 160
79 #define DELAY_FAST_CLK_SWITCH 3
80 #define DELAY_SLOW_CLK_SWITCH 300
81 #define DELAY_8M_ENABLE 50
83 /* Number of 8M/256 clock cycles to use for XTAL frequency estimation.
84 * 10 cycles will take approximately 300 microseconds.
86 #define XTAL_FREQ_EST_CYCLES 10
89 static void rtc_clk_32k_enable_internal(int dac, int dres, int dbias)
91 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
92 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG,
93 RTC_IO_X32P_RDE | RTC_IO_X32P_RUE | RTC_IO_X32N_RUE |
94 RTC_IO_X32N_RDE | RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
95 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DAC_XTAL_32K, dac);
96 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DRES_XTAL_32K, dres);
97 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, dbias);
98 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
101 void rtc_clk_32k_enable(bool enable)
104 rtc_clk_32k_enable_internal(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DBIAS_VAL);
106 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
110 void rtc_clk_32k_bootstrap()
112 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
113 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_RUE | RTC_IO_X32N_RDE);
114 ets_delay_us(XTAL_32K_BOOTSTRAP_TIME_US);
115 rtc_clk_32k_enable_internal(XTAL_32K_BOOTSTRAP_DAC_VAL,
116 XTAL_32K_BOOTSTRAP_DRES_VAL, XTAL_32K_BOOTSTRAP_DBIAS_VAL);
119 bool rtc_clk_32k_enabled()
121 return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K) != 0;
124 void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
127 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
128 /* no need to wait once enabled by software */
129 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1);
131 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
133 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
135 ets_delay_us(DELAY_8M_ENABLE);
137 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
138 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
142 bool rtc_clk_8m_enabled()
144 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
147 bool rtc_clk_8md256_enabled()
149 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
152 void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div)
154 REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD, enable ? 0 : 1);
155 REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0);
156 REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD, enable ? 0 : 1);
159 REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) != RTC_CNTL_SOC_CLK_SEL_PLL) {
160 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
164 uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1;
165 uint32_t is_rev0 = (GET_PERI_REG_BITS2(EFUSE_BLK0_RDATA3_REG, 1, 15) == 0);
169 sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0;
171 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM2, sdm2);
172 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM0, sdm0);
173 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM1, sdm1);
174 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
175 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, sdm_stop_val_2);
176 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
179 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
180 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
181 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
183 /* wait for calibration end */
184 while (!(I2C_READREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_CAL_END))) {
185 /* use ets_delay_us so the RTC bus doesn't get flooded */
191 void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
193 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
194 ets_delay_us(DELAY_SLOW_CLK_SWITCH);
197 rtc_slow_freq_t rtc_clk_slow_freq_get()
199 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
202 uint32_t rtc_clk_slow_freq_get_hz()
204 switch(rtc_clk_slow_freq_get()) {
205 case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
206 case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K;
207 case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256;
212 void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)
214 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq);
215 ets_delay_us(DELAY_FAST_CLK_SWITCH);
218 rtc_fast_freq_t rtc_clk_fast_freq_get()
220 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
223 void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_cpu_freq_t cpu_freq)
232 if (cpu_freq != RTC_CPU_FREQ_240M) {
233 /* Configure 320M PLL */
235 case RTC_XTAL_FREQ_40M:
243 case RTC_XTAL_FREQ_26M:
251 case RTC_XTAL_FREQ_24M:
268 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_320M);
269 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_320M);
271 /* Raise the voltage */
272 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V25);
273 ets_delay_us(DELAY_PLL_DBIAS_RAISE);
274 /* Configure 480M PLL */
276 case RTC_XTAL_FREQ_40M:
284 case RTC_XTAL_FREQ_26M:
292 case RTC_XTAL_FREQ_24M:
309 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_480M);
310 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_480M);
313 uint8_t i2c_bbpll_lref = (lref << 7) | (div10_8 << 4) | (div_ref);
314 uint8_t i2c_bbpll_div_7_0 = div7_0;
315 uint8_t i2c_bbpll_dcur = (bw << 6) | dcur;
316 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref);
317 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
318 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
319 uint32_t delay_pll_en = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ?
320 DELAY_PLL_ENABLE_WITH_150K : DELAY_PLL_ENABLE_WITH_32K;
321 ets_delay_us(delay_pll_en);
324 void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq)
326 rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
327 /* Switch CPU to XTAL frequency first */
328 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V10);
329 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
330 REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0);
331 ets_update_cpu_frequency(xtal_freq);
332 uint32_t delay_xtal_switch = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ?
333 DELAY_CPU_FREQ_SWITCH_TO_XTAL_WITH_150K : DELAY_CPU_FREQ_SWITCH_TO_XTAL_WITH_32K;
334 ets_delay_us(delay_xtal_switch);
335 REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
336 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
337 RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
338 RTC_CNTL_BBPLL_I2C_FORCE_PD);
339 rtc_clk_apb_freq_update(xtal_freq * MHZ);
341 /* is APLL under force power down? */
342 uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
344 /* then also power down the internal I2C bus */
345 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
347 /* now switch to the desired frequency */
348 if (cpu_freq == RTC_CPU_FREQ_XTAL) {
349 /* already at XTAL, nothing to do */
350 } else if (cpu_freq == RTC_CPU_FREQ_2M) {
351 /* set up divider to produce 2MHz from XTAL */
352 REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, (xtal_freq / 2) - 1);
353 ets_update_cpu_frequency(2);
354 rtc_clk_apb_freq_update(2 * MHZ);
355 /* lower the voltage */
356 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V00);
358 /* use PLL as clock source */
359 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
360 RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD |
361 RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
362 rtc_clk_bbpll_set(xtal_freq, cpu_freq);
363 if (cpu_freq == RTC_CPU_FREQ_80M) {
364 REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
365 ets_update_cpu_frequency(80);
366 } else if (cpu_freq == RTC_CPU_FREQ_160M) {
367 REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1);
368 ets_update_cpu_frequency(160);
369 } else if (cpu_freq == RTC_CPU_FREQ_240M) {
370 REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2);
371 ets_update_cpu_frequency(240);
373 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
374 ets_delay_us(DELAY_CPU_FREQ_SWITCH_TO_PLL);
375 rtc_clk_apb_freq_update(80 * MHZ);
379 rtc_cpu_freq_t rtc_clk_cpu_freq_get()
381 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
382 switch (soc_clk_sel) {
383 case RTC_CNTL_SOC_CLK_SEL_XTL: {
384 uint32_t pre_div = REG_GET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT);
386 return RTC_CPU_FREQ_XTAL;
387 } else if (pre_div == rtc_clk_xtal_freq_get() / 2 - 1) {
388 return RTC_CPU_FREQ_2M;
390 assert(false && "unsupported frequency");
394 case RTC_CNTL_SOC_CLK_SEL_PLL: {
395 uint32_t cpuperiod_sel = REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
396 if (cpuperiod_sel == 0) {
397 return RTC_CPU_FREQ_80M;
398 } else if (cpuperiod_sel == 1) {
399 return RTC_CPU_FREQ_160M;
400 } else if (cpuperiod_sel == 2) {
401 return RTC_CPU_FREQ_240M;
403 assert(false && "unsupported frequency");
407 case RTC_CNTL_SOC_CLK_SEL_APLL:
408 case RTC_CNTL_SOC_CLK_SEL_8M:
410 assert(false && "unsupported frequency");
412 return RTC_CNTL_SOC_CLK_SEL_XTL;
415 uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq)
418 case RTC_CPU_FREQ_XTAL:
419 return ((uint32_t) rtc_clk_xtal_freq_get()) * MHZ;
420 case RTC_CPU_FREQ_2M:
422 case RTC_CPU_FREQ_80M:
424 case RTC_CPU_FREQ_160M:
426 case RTC_CPU_FREQ_240M:
429 assert(false && "invalid rtc_cpu_freq_t value");
434 /* Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in
435 * lower and upper 16-bit halves. These are the routines to work with such a
438 static bool clk_val_is_valid(uint32_t val) {
439 return (val & 0xffff) == ((val >> 16) & 0xffff) &&
444 static uint32_t reg_val_to_clk_val(uint32_t val) {
445 return val & UINT16_MAX;
448 static uint32_t clk_val_to_reg_val(uint32_t val) {
449 return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16);
452 rtc_xtal_freq_t rtc_clk_xtal_freq_get()
454 /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */
455 uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
456 if (!clk_val_is_valid(xtal_freq_reg)) {
457 SOC_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value: 0x%08x", xtal_freq_reg);
458 return RTC_XTAL_FREQ_AUTO;
460 return reg_val_to_clk_val(xtal_freq_reg);
463 void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
465 WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
468 static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate()
470 uint64_t cal_val = rtc_clk_cal_ratio(RTC_CAL_8MD256, XTAL_FREQ_EST_CYCLES);
471 /* cal_val contains period of 8M/256 clock in XTAL clock cycles
472 * (shifted by RTC_CLK_CAL_FRACT bits).
473 * Xtal frequency will be (cal_val * 8M / 256) / 2^19
475 uint32_t freq_mhz = (cal_val * (RTC_FAST_CLK_FREQ_APPROX / MHZ) / 256 ) >> RTC_CLK_CAL_FRACT;
476 /* Guess the XTAL type. For now, only 40 and 26MHz are supported.
480 return RTC_XTAL_FREQ_26M;
482 SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 26 MHz", freq_mhz);
483 return RTC_XTAL_FREQ_26M;
485 SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 40 MHz", freq_mhz);
486 return RTC_XTAL_FREQ_40M;
488 return RTC_XTAL_FREQ_40M;
490 SOC_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz);
491 return RTC_XTAL_FREQ_AUTO;
495 void rtc_clk_apb_freq_update(uint32_t apb_freq)
497 WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
500 uint32_t rtc_clk_apb_freq_get()
502 return reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
506 void rtc_clk_init(rtc_clk_config_t cfg)
508 /* If we get a TG WDT system reset while running at 240MHz,
509 * DPORT_CPUPERIOD_SEL register will be reset to 0 resulting in 120MHz
510 * APB and CPU frequencies after reset. This will cause issues with XTAL
511 * frequency estimation, so we switch to XTAL frequency first.
513 * Ideally we would only do this if RTC_CNTL_SOC_CLK_SEL == PLL and
514 * PLL is configured for 480M, but it takes less time to switch to 40M and
515 * run the following code than querying the PLL does.
517 if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) == RTC_CNTL_SOC_CLK_SEL_PLL) {
518 rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL);
521 /* Set tuning parameters for 8M and 150k clocks.
522 * Note: this doesn't attempt to set the clocks to precise frequencies.
523 * Instead, we calibrate these clocks against XTAL frequency later, when necessary.
524 * - SCK_DCAP value controls tuning of 150k clock.
525 * The higher the value of DCAP is, the lower is the frequency.
526 * - CK8M_DFREQ value controls tuning of 8M clock.
527 * CLK_8M_DFREQ constant gives the best temperature characteristics.
529 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
530 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
532 /* Configure 8M clock division */
533 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, cfg.clk_8m_div);
535 /* Enable the internal bus used to configure PLLs */
536 SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
537 CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M);
539 /* Estimate XTAL frequency if requested */
540 rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
541 if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
542 if (clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) {
543 /* XTAL frequency has already been set, use existing value */
544 xtal_freq = rtc_clk_xtal_freq_get();
546 /* Not set yet, estimate XTAL frequency based on RTC_FAST_CLK */
547 xtal_freq = rtc_clk_xtal_freq_estimate();
548 if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
549 SOC_LOGW(TAG, "Can't estimate XTAL frequency, assuming 26MHz");
550 xtal_freq = RTC_XTAL_FREQ_26M;
554 rtc_clk_xtal_freq_update(xtal_freq);
555 rtc_clk_apb_freq_update(xtal_freq * MHZ);
556 /* Set CPU frequency */
557 rtc_clk_cpu_freq_set(cfg.cpu_freq);
559 /* Slow & fast clocks setup */
560 if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
561 rtc_clk_32k_enable(true);
563 if (cfg.fast_freq == RTC_FAST_FREQ_8M) {
564 bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256;
565 rtc_clk_8m_enable(true, need_8md256);
567 rtc_clk_fast_freq_set(cfg.fast_freq);
568 rtc_clk_slow_freq_set(cfg.slow_freq);
571 /* Name used in libphy.a:phy_chip_v7.o
572 * TODO: update the library to use rtc_clk_xtal_freq_get
574 rtc_xtal_freq_t rtc_get_xtal() __attribute__((alias("rtc_clk_xtal_freq_get")));