1 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
19 #include "rom/ets_sys.h"
23 #include "soc/rtc_cntl_reg.h"
24 #include "soc/rtc_io_reg.h"
25 #include "soc/sens_reg.h"
26 #include "soc/dport_reg.h"
27 #include "soc/efuse_reg.h"
28 #include "soc/apb_ctrl_reg.h"
29 #include "i2c_rtc_clk.h"
31 #include "sdkconfig.h"
35 static const char* TAG = "rtc_clk";
37 /* Various constants related to the analog internals of the chip.
38 * Defined here because they don't have any use outside of this file.
41 #define BBPLL_ENDIV5_VAL_320M 0x43
42 #define BBPLL_BBADC_DSMP_VAL_320M 0x84
43 #define BBPLL_ENDIV5_VAL_480M 0xc3
44 #define BBPLL_BBADC_DSMP_VAL_480M 0x74
46 #define APLL_SDM_STOP_VAL_1 0x09
47 #define APLL_SDM_STOP_VAL_2_REV0 0x69
48 #define APLL_SDM_STOP_VAL_2_REV1 0x49
50 #define APLL_CAL_DELAY_1 0x0f
51 #define APLL_CAL_DELAY_2 0x3f
52 #define APLL_CAL_DELAY_3 0x1f
54 #define XTAL_32K_DAC_VAL 1
55 #define XTAL_32K_DRES_VAL 3
56 #define XTAL_32K_DBIAS_VAL 0
58 /* Delays for various clock sources to be enabled/switched.
59 * All values are in microseconds.
60 * TODO: some of these are excessive, and should be reduced.
62 #define DELAY_CPU_FREQ_SWITCH_TO_XTAL 80
63 #define DELAY_CPU_FREQ_SWITCH_TO_PLL 10
64 #define DELAY_PLL_DBIAS_RAISE 3
65 #define DELAY_PLL_ENABLE 80
66 #define DELAY_FAST_CLK_SWITCH 3
67 #define DELAY_SLOW_CLK_SWITCH 300
68 #define DELAY_8M_ENABLE 50
70 /* Number of 8M/256 clock cycles to use for XTAL frequency estimation.
71 * 10 cycles will take approximately 300 microseconds.
73 #define XTAL_FREQ_EST_CYCLES 10
76 void rtc_clk_32k_enable(bool enable)
79 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
80 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG,
81 RTC_IO_X32P_RDE | RTC_IO_X32P_RUE | RTC_IO_X32N_RUE |
82 RTC_IO_X32N_RDE | RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
83 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DAC_XTAL_32K, XTAL_32K_DAC_VAL);
84 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DRES_XTAL_32K, XTAL_32K_DRES_VAL);
85 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, XTAL_32K_DBIAS_VAL);
86 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
88 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
92 bool rtc_clk_32k_enabled()
94 return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K) != 0;
97 void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
100 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
101 /* no need to wait once enabled by software */
102 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1);
104 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
106 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
108 ets_delay_us(DELAY_8M_ENABLE);
110 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
111 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
115 bool rtc_clk_8m_enabled()
117 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
120 bool rtc_clk_8md256_enabled()
122 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
125 void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div)
127 REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD, enable ? 0 : 1);
128 REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0);
129 REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD, enable ? 0 : 1);
132 REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) != RTC_CNTL_SOC_CLK_SEL_PLL) {
133 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
137 uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1;
138 uint32_t is_rev0 = (GET_PERI_REG_BITS2(EFUSE_BLK0_RDATA3_REG, 1, 15) == 0);
142 sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0;
144 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM2, sdm2);
145 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM0, sdm0);
146 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM1, sdm1);
147 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
148 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, sdm_stop_val_2);
149 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
152 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
153 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
154 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
156 /* wait for calibration end */
157 while (!(I2C_READREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_CAL_END))) {
158 /* use ets_delay_us so the RTC bus doesn't get flooded */
164 void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
166 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
167 ets_delay_us(DELAY_SLOW_CLK_SWITCH);
170 rtc_slow_freq_t rtc_clk_slow_freq_get()
172 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
176 void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)
178 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq);
179 ets_delay_us(DELAY_FAST_CLK_SWITCH);
182 rtc_fast_freq_t rtc_clk_fast_freq_get()
184 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
187 void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_cpu_freq_t cpu_freq)
196 if (cpu_freq != RTC_CPU_FREQ_240M) {
197 /* Configure 320M PLL */
199 case RTC_XTAL_FREQ_40M:
207 case RTC_XTAL_FREQ_26M:
215 case RTC_XTAL_FREQ_24M:
232 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_320M);
233 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_320M);
235 /* Raise the voltage */
236 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V25);
237 ets_delay_us(DELAY_PLL_DBIAS_RAISE);
238 /* Configure 480M PLL */
240 case RTC_XTAL_FREQ_40M:
248 case RTC_XTAL_FREQ_26M:
256 case RTC_XTAL_FREQ_24M:
273 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_480M);
274 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_480M);
277 uint8_t i2c_bbpll_lref = (lref << 7) | (div10_8 << 4) | (div_ref);
278 uint8_t i2c_bbpll_div_7_0 = div7_0;
279 uint8_t i2c_bbpll_dcur = (bw << 6) | dcur;
280 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref);
281 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
282 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
283 ets_delay_us(DELAY_PLL_ENABLE);
286 void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq)
288 rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
289 /* Switch CPU to XTAL frequency first */
290 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V10);
291 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
292 REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0);
293 ets_update_cpu_frequency(xtal_freq);
294 ets_delay_us(DELAY_CPU_FREQ_SWITCH_TO_XTAL);
295 REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
296 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
297 RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
298 RTC_CNTL_BBPLL_I2C_FORCE_PD);
299 rtc_clk_apb_freq_update(xtal_freq * MHZ);
301 /* is APLL under force power down? */
302 uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
304 /* then also power down the internal I2C bus */
305 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
307 /* now switch to the desired frequency */
308 if (cpu_freq == RTC_CPU_FREQ_XTAL) {
309 /* already at XTAL, nothing to do */
310 } else if (cpu_freq == RTC_CPU_FREQ_2M) {
311 /* set up divider to produce 2MHz from XTAL */
312 REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, (xtal_freq / 2) - 1);
313 ets_update_cpu_frequency(2);
314 rtc_clk_apb_freq_update(2 * MHZ);
315 /* lower the voltage */
316 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V00);
318 /* use PLL as clock source */
319 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
320 RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD |
321 RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
322 rtc_clk_bbpll_set(xtal_freq, cpu_freq);
323 if (cpu_freq == RTC_CPU_FREQ_80M) {
324 REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
325 ets_update_cpu_frequency(80);
326 } else if (cpu_freq == RTC_CPU_FREQ_160M) {
327 REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1);
328 ets_update_cpu_frequency(160);
329 } else if (cpu_freq == RTC_CPU_FREQ_240M) {
330 REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2);
331 ets_update_cpu_frequency(240);
333 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
334 ets_delay_us(DELAY_CPU_FREQ_SWITCH_TO_PLL);
335 rtc_clk_apb_freq_update(80 * MHZ);
339 rtc_cpu_freq_t rtc_clk_cpu_freq_get()
341 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
342 switch (soc_clk_sel) {
343 case RTC_CNTL_SOC_CLK_SEL_XTL: {
344 uint32_t pre_div = REG_GET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT);
346 return RTC_CPU_FREQ_XTAL;
347 } else if (pre_div == rtc_clk_xtal_freq_get() / 2 - 1) {
348 return RTC_CPU_FREQ_2M;
350 assert(false && "unsupported frequency");
354 case RTC_CNTL_SOC_CLK_SEL_PLL: {
355 uint32_t cpuperiod_sel = REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
356 if (cpuperiod_sel == 0) {
357 return RTC_CPU_FREQ_80M;
358 } else if (cpuperiod_sel == 1) {
359 return RTC_CPU_FREQ_160M;
360 } else if (cpuperiod_sel == 2) {
361 return RTC_CPU_FREQ_240M;
363 assert(false && "unsupported frequency");
367 case RTC_CNTL_SOC_CLK_SEL_APLL:
368 case RTC_CNTL_SOC_CLK_SEL_8M:
370 assert(false && "unsupported frequency");
372 return RTC_CNTL_SOC_CLK_SEL_XTL;
375 uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq)
378 case RTC_CPU_FREQ_XTAL:
379 return ((uint32_t) rtc_clk_xtal_freq_get()) * MHZ;
380 case RTC_CPU_FREQ_2M:
382 case RTC_CPU_FREQ_80M:
384 case RTC_CPU_FREQ_160M:
386 case RTC_CPU_FREQ_240M:
389 assert(false && "invalid rtc_cpu_freq_t value");
394 /* Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in
395 * lower and upper 16-bit halves. These are the routines to work with such a
398 static bool clk_val_is_valid(uint32_t val) {
399 return (val & 0xffff) == ((val >> 16) & 0xffff) &&
404 static uint32_t reg_val_to_clk_val(uint32_t val) {
405 return val & UINT16_MAX;
408 static uint32_t clk_val_to_reg_val(uint32_t val) {
409 return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16);
412 rtc_xtal_freq_t rtc_clk_xtal_freq_get()
414 /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */
415 uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
416 if (!clk_val_is_valid(xtal_freq_reg)) {
417 SOC_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value: 0x%08x", xtal_freq_reg);
418 return RTC_XTAL_FREQ_AUTO;
420 return reg_val_to_clk_val(xtal_freq_reg);
423 void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
425 WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
428 static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate()
430 uint64_t cal_val = rtc_clk_cal_ratio(RTC_CAL_8MD256, XTAL_FREQ_EST_CYCLES);
431 /* cal_val contains period of 8M/256 clock in XTAL clock cycles
432 * (shifted by RTC_CLK_CAL_FRACT bits).
433 * Xtal frequency will be (cal_val * 8M / 256) / 2^19
435 uint32_t freq_mhz = (cal_val * (RTC_FAST_CLK_FREQ_APPROX / MHZ) / 256 ) >> RTC_CLK_CAL_FRACT;
436 /* Guess the XTAL type. For now, only 40 and 26MHz are supported.
440 return RTC_XTAL_FREQ_26M;
442 SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 26 MHz", freq_mhz);
443 return RTC_XTAL_FREQ_26M;
445 SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 40 MHz", freq_mhz);
446 return RTC_XTAL_FREQ_40M;
448 return RTC_XTAL_FREQ_40M;
450 SOC_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz);
451 return RTC_XTAL_FREQ_AUTO;
455 void rtc_clk_apb_freq_update(uint32_t apb_freq)
457 WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
460 uint32_t rtc_clk_apb_freq_get()
462 return reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
466 void rtc_clk_init(rtc_clk_config_t cfg)
468 /* If we get a TG WDT system reset while running at 240MHz,
469 * DPORT_CPUPERIOD_SEL register will be reset to 0 resulting in 120MHz
470 * APB and CPU frequencies after reset. This will cause issues with XTAL
471 * frequency estimation, so we switch to XTAL frequency first.
473 * Ideally we would only do this if RTC_CNTL_SOC_CLK_SEL == PLL and
474 * PLL is configured for 480M, but it takes less time to switch to 40M and
475 * run the following code than querying the PLL does.
477 if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) == RTC_CNTL_SOC_CLK_SEL_PLL) {
478 rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL);
481 /* Set tuning parameters for 8M and 150k clocks.
482 * Note: this doesn't attempt to set the clocks to precise frequencies.
483 * Instead, we calibrate these clocks against XTAL frequency later, when necessary.
484 * - SCK_DCAP value controls tuning of 150k clock.
485 * The higher the value of DCAP is, the lower is the frequency.
486 * - CK8M_DFREQ value controls tuning of 8M clock.
487 * CLK_8M_DFREQ constant gives the best temperature characteristics.
489 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
490 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
492 /* Configure 8M clock division */
493 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, cfg.clk_8m_div);
495 /* Enable the internal bus used to configure PLLs */
496 SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
497 CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M);
499 /* Estimate XTAL frequency if requested */
500 rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
501 if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
502 if (clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) {
503 /* XTAL frequency has already been set, use existing value */
504 xtal_freq = rtc_clk_xtal_freq_get();
506 /* Not set yet, estimate XTAL frequency based on RTC_FAST_CLK */
507 xtal_freq = rtc_clk_xtal_freq_estimate();
508 if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
509 SOC_LOGW(TAG, "Can't estimate XTAL frequency, assuming 26MHz");
510 xtal_freq = RTC_XTAL_FREQ_26M;
514 rtc_clk_xtal_freq_update(xtal_freq);
515 rtc_clk_apb_freq_update(xtal_freq * MHZ);
516 /* Set CPU frequency */
517 rtc_clk_cpu_freq_set(cfg.cpu_freq);
519 /* Slow & fast clocks setup */
520 if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
521 rtc_clk_32k_enable(false);
523 if (cfg.fast_freq == RTC_FAST_FREQ_8M) {
524 bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256;
525 rtc_clk_8m_enable(true, need_8md256);
527 rtc_clk_fast_freq_set(cfg.fast_freq);
528 rtc_clk_slow_freq_set(cfg.slow_freq);
531 /* Name used in libphy.a:phy_chip_v7.o
532 * TODO: update the library to use rtc_clk_xtal_freq_get
534 rtc_xtal_freq_t rtc_get_xtal() __attribute__((alias("rtc_clk_xtal_freq_get")));