1 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
19 #include "rom/ets_sys.h"
23 #include "soc/rtc_cntl_reg.h"
24 #include "soc/rtc_io_reg.h"
25 #include "soc/sens_reg.h"
26 #include "soc/dport_reg.h"
27 #include "soc/efuse_reg.h"
28 #include "soc/apb_ctrl_reg.h"
29 #include "i2c_rtc_clk.h"
31 #include "sdkconfig.h"
35 static const char* TAG = "rtc_clk";
37 /* Various constants related to the analog internals of the chip.
38 * Defined here because they don't have any use outside of this file.
41 #define BBPLL_ENDIV5_VAL_320M 0x43
42 #define BBPLL_BBADC_DSMP_VAL_320M 0x84
43 #define BBPLL_ENDIV5_VAL_480M 0xc3
44 #define BBPLL_BBADC_DSMP_VAL_480M 0x74
46 #define APLL_SDM_STOP_VAL_1 0x09
47 #define APLL_SDM_STOP_VAL_2_REV0 0x69
48 #define APLL_SDM_STOP_VAL_2_REV1 0x49
50 #define APLL_CAL_DELAY_1 0x0f
51 #define APLL_CAL_DELAY_2 0x3f
52 #define APLL_CAL_DELAY_3 0x1f
54 #define XTAL_32K_DAC_VAL 1
55 #define XTAL_32K_DRES_VAL 3
56 #define XTAL_32K_DBIAS_VAL 0
58 /* Delays for various clock sources to be enabled/switched.
59 * All values are in microseconds.
60 * TODO: some of these are excessive, and should be reduced.
62 #define DELAY_CPU_FREQ_SWITCH_TO_XTAL 80
63 #define DELAY_CPU_FREQ_SWITCH_TO_PLL 10
64 #define DELAY_PLL_DBIAS_RAISE 3
65 #define DELAY_PLL_ENABLE 80
66 #define DELAY_FAST_CLK_SWITCH 3
67 #define DELAY_SLOW_CLK_SWITCH 300
68 #define DELAY_8M_ENABLE 50
71 void rtc_clk_32k_enable(bool enable)
74 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
75 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG,
76 RTC_IO_X32P_RDE | RTC_IO_X32P_RUE | RTC_IO_X32N_RUE |
77 RTC_IO_X32N_RDE | RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
78 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DAC_XTAL_32K, XTAL_32K_DAC_VAL);
79 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DRES_XTAL_32K, XTAL_32K_DRES_VAL);
80 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, XTAL_32K_DBIAS_VAL);
81 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
83 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
87 bool rtc_clk_32k_enabled()
89 return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K) != 0;
92 void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
95 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
96 /* no need to wait once enabled by software */
97 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1);
99 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
101 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
103 ets_delay_us(DELAY_8M_ENABLE);
105 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
106 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
110 bool rtc_clk_8m_enabled()
112 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
115 bool rtc_clk_8md256_enabled()
117 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
120 void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div)
122 REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD, enable ? 0 : 1);
123 REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0);
124 REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD, enable ? 0 : 1);
127 REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) != RTC_CNTL_SOC_CLK_SEL_PLL) {
128 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
132 uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1;
133 uint32_t is_rev0 = (GET_PERI_REG_BITS2(EFUSE_BLK0_RDATA3_REG, 1, 15) == 0);
137 sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0;
139 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM2, sdm2);
140 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM0, sdm0);
141 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM1, sdm1);
142 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
143 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, sdm_stop_val_2);
144 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
147 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
148 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
149 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
151 /* wait for calibration end */
152 while (!(I2C_READREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_CAL_END))) {
153 /* use ets_delay_us so the RTC bus doesn't get flooded */
159 void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
161 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
162 ets_delay_us(DELAY_SLOW_CLK_SWITCH);
165 rtc_slow_freq_t rtc_clk_slow_freq_get()
167 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
171 void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)
173 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq);
174 ets_delay_us(DELAY_FAST_CLK_SWITCH);
177 rtc_fast_freq_t rtc_clk_fast_freq_get()
179 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
182 void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_cpu_freq_t cpu_freq)
191 if (cpu_freq != RTC_CPU_FREQ_240M) {
192 /* Configure 320M PLL */
194 case RTC_XTAL_FREQ_40M:
202 case RTC_XTAL_FREQ_26M:
210 case RTC_XTAL_FREQ_24M:
227 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_320M);
228 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_320M);
230 /* Raise the voltage */
231 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V25);
232 ets_delay_us(DELAY_PLL_DBIAS_RAISE);
233 /* Configure 480M PLL */
235 case RTC_XTAL_FREQ_40M:
243 case RTC_XTAL_FREQ_26M:
251 case RTC_XTAL_FREQ_24M:
268 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_480M);
269 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_480M);
272 uint8_t i2c_bbpll_lref = (lref << 7) | (div10_8 << 4) | (div_ref);
273 uint8_t i2c_bbpll_div_7_0 = div7_0;
274 uint8_t i2c_bbpll_dcur = (bw << 6) | dcur;
275 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref);
276 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
277 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
278 ets_delay_us(DELAY_PLL_ENABLE);
281 void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq)
283 rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
284 /* Switch CPU to XTAL frequency first */
285 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V10);
286 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
287 REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0);
288 ets_update_cpu_frequency(xtal_freq);
289 ets_delay_us(DELAY_CPU_FREQ_SWITCH_TO_XTAL);
290 REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
291 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
292 RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
293 RTC_CNTL_BBPLL_I2C_FORCE_PD);
294 rtc_clk_apb_freq_update(xtal_freq * MHZ);
296 /* is APLL under force power down? */
297 uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
299 /* then also power down the internal I2C bus */
300 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
302 /* now switch to the desired frequency */
303 if (cpu_freq == RTC_CPU_FREQ_XTAL) {
304 /* already at XTAL, nothing to do */
305 } else if (cpu_freq == RTC_CPU_FREQ_2M) {
306 /* set up divider to produce 2MHz from XTAL */
307 REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, (xtal_freq / 2) - 1);
308 ets_update_cpu_frequency(2);
309 rtc_clk_apb_freq_update(2 * MHZ);
310 /* lower the voltage */
311 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V00);
313 /* use PLL as clock source */
314 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
315 RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD |
316 RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
317 rtc_clk_bbpll_set(xtal_freq, cpu_freq);
318 if (cpu_freq == RTC_CPU_FREQ_80M) {
319 REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
320 ets_update_cpu_frequency(80);
321 } else if (cpu_freq == RTC_CPU_FREQ_160M) {
322 REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1);
323 ets_update_cpu_frequency(160);
324 } else if (cpu_freq == RTC_CPU_FREQ_240M) {
325 REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2);
326 ets_update_cpu_frequency(240);
328 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
329 ets_delay_us(DELAY_CPU_FREQ_SWITCH_TO_PLL);
330 rtc_clk_apb_freq_update(80 * MHZ);
334 rtc_cpu_freq_t rtc_clk_cpu_freq_get()
336 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
337 switch (soc_clk_sel) {
338 case RTC_CNTL_SOC_CLK_SEL_XTL: {
339 uint32_t pre_div = REG_GET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT);
341 return RTC_CPU_FREQ_XTAL;
342 } else if (pre_div == rtc_clk_xtal_freq_get() / 2 - 1) {
343 return RTC_CPU_FREQ_2M;
345 assert(false && "unsupported frequency");
349 case RTC_CNTL_SOC_CLK_SEL_PLL: {
350 uint32_t cpuperiod_sel = REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
351 if (cpuperiod_sel == 0) {
352 return RTC_CPU_FREQ_80M;
353 } else if (cpuperiod_sel == 1) {
354 return RTC_CPU_FREQ_160M;
355 } else if (cpuperiod_sel == 2) {
356 return RTC_CPU_FREQ_240M;
358 assert(false && "unsupported frequency");
362 case RTC_CNTL_SOC_CLK_SEL_APLL:
363 case RTC_CNTL_SOC_CLK_SEL_8M:
365 assert(false && "unsupported frequency");
367 return RTC_CNTL_SOC_CLK_SEL_XTL;
370 uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq)
373 case RTC_CPU_FREQ_XTAL:
374 return ((uint32_t) rtc_clk_xtal_freq_get()) * MHZ;
375 case RTC_CPU_FREQ_2M:
377 case RTC_CPU_FREQ_80M:
379 case RTC_CPU_FREQ_160M:
381 case RTC_CPU_FREQ_240M:
384 assert(false && "invalid rtc_cpu_freq_t value");
389 /* Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in
390 * lower and upper 16-bit halves. These are the routines to work with such a
393 static bool clk_val_is_valid(uint32_t val) {
394 return (val & 0xffff) == ((val >> 16) & 0xffff) &&
399 static uint32_t reg_val_to_clk_val(uint32_t val) {
400 return val & UINT16_MAX;
403 static uint32_t clk_val_to_reg_val(uint32_t val) {
404 return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16);
407 rtc_xtal_freq_t rtc_clk_xtal_freq_get()
409 /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */
410 uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
411 if (!clk_val_is_valid(xtal_freq_reg)) {
412 SOC_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value: 0x%08x", xtal_freq_reg);
413 return RTC_XTAL_FREQ_AUTO;
415 return reg_val_to_clk_val(xtal_freq_reg);
418 void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
420 WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
423 static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate()
425 /* ROM startup code estimates XTAL frequency using an 8MD256 clock and stores
426 * the value into RTC_APB_FREQ_REG. The value is in Hz, right shifted by 12.
427 * Use this value to guess the real XTAL frequency.
429 * TODO: make this more robust by calibrating again after setting
430 * RTC_CNTL_CK8M_DFREQ.
432 uint32_t apb_freq_reg = READ_PERI_REG(RTC_APB_FREQ_REG);
433 if (!clk_val_is_valid(apb_freq_reg)) {
434 SOC_LOGW(TAG, "invalid RTC_APB_FREQ_REG value: 0x%08x", apb_freq_reg);
435 return RTC_XTAL_FREQ_AUTO;
437 uint32_t freq_mhz = (reg_val_to_clk_val(apb_freq_reg) << 12) / MHZ;
438 /* Guess the XTAL type. For now, only 40 and 26MHz are supported.
442 return RTC_XTAL_FREQ_26M;
444 SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 26 MHz", freq_mhz);
445 return RTC_XTAL_FREQ_26M;
447 SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 40 MHz", freq_mhz);
448 return RTC_XTAL_FREQ_40M;
450 return RTC_XTAL_FREQ_40M;
452 SOC_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz);
453 return RTC_XTAL_FREQ_AUTO;
457 void rtc_clk_apb_freq_update(uint32_t apb_freq)
459 WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
462 uint32_t rtc_clk_apb_freq_get()
464 return reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
468 void rtc_clk_init(rtc_clk_config_t cfg)
470 /* Set tuning parameters for 8M and 150k clocks.
471 * Note: this doesn't attempt to set the clocks to precise frequencies.
472 * Instead, we calibrate these clocks against XTAL frequency later, when necessary.
473 * - SCK_DCAP value controls tuning of 150k clock.
474 * The higher the value of DCAP is, the lower is the frequency.
475 * - CK8M_DFREQ value controls tuning of 8M clock.
476 * CLK_8M_DFREQ constant gives the best temperature characteristics.
478 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
479 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
481 /* Configure 8M clock division */
482 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, cfg.clk_8m_div);
484 /* Enable the internal bus used to configure PLLs */
485 SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
486 CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M);
488 /* Estimate XTAL frequency if requested */
489 rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
490 if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
491 xtal_freq = rtc_clk_xtal_freq_estimate();
492 if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
493 SOC_LOGW(TAG, "Can't estimate XTAL frequency, assuming 26MHz");
494 xtal_freq = RTC_XTAL_FREQ_26M;
497 rtc_clk_xtal_freq_update(xtal_freq);
498 rtc_clk_apb_freq_update(xtal_freq * MHZ);
499 /* Set CPU frequency */
500 rtc_clk_cpu_freq_set(cfg.cpu_freq);
502 /* Slow & fast clocks setup */
503 if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
504 rtc_clk_32k_enable(false);
506 if (cfg.fast_freq == RTC_FAST_FREQ_8M) {
507 bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256;
508 rtc_clk_8m_enable(true, need_8md256);
510 rtc_clk_fast_freq_set(cfg.fast_freq);
511 rtc_clk_slow_freq_set(cfg.slow_freq);
514 /* Name used in libphy.a:phy_chip_v7.o
515 * TODO: update the library to use rtc_clk_xtal_freq_get
517 rtc_xtal_freq_t rtc_get_xtal() __attribute__((alias("rtc_clk_xtal_freq_get")));
520 /* Referenced in librtc.a:rtc.o.
523 void rtc_uart_div_modify(int latch)
528 /* Referenced in librtc.a:rtc.o.
531 void rtc_uart_tx_wait_idle(int uart)