1 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
19 #include "rom/ets_sys.h"
23 #include "soc/rtc_cntl_reg.h"
24 #include "soc/rtc_io_reg.h"
25 #include "soc/sens_reg.h"
26 #include "soc/dport_reg.h"
27 #include "soc/efuse_reg.h"
28 #include "soc/apb_ctrl_reg.h"
29 #include "i2c_rtc_clk.h"
31 #include "sdkconfig.h"
36 /* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting */
37 #define RTC_FAST_CLK_FREQ_8M 8500000
38 #define RTC_SLOW_CLK_FREQ_150K 150000
39 #define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256)
40 #define RTC_SLOW_CLK_FREQ_32K 32768
42 static const char* TAG = "rtc_clk";
44 /* Various constants related to the analog internals of the chip.
45 * Defined here because they don't have any use outside of this file.
48 #define BBPLL_ENDIV5_VAL_320M 0x43
49 #define BBPLL_BBADC_DSMP_VAL_320M 0x84
50 #define BBPLL_ENDIV5_VAL_480M 0xc3
51 #define BBPLL_BBADC_DSMP_VAL_480M 0x74
53 #define APLL_SDM_STOP_VAL_1 0x09
54 #define APLL_SDM_STOP_VAL_2_REV0 0x69
55 #define APLL_SDM_STOP_VAL_2_REV1 0x49
57 #define APLL_CAL_DELAY_1 0x0f
58 #define APLL_CAL_DELAY_2 0x3f
59 #define APLL_CAL_DELAY_3 0x1f
61 #define XTAL_32K_DAC_VAL 1
62 #define XTAL_32K_DRES_VAL 3
63 #define XTAL_32K_DBIAS_VAL 0
65 #define XTAL_32K_BOOTSTRAP_DAC_VAL 3
66 #define XTAL_32K_BOOTSTRAP_DRES_VAL 3
67 #define XTAL_32K_BOOTSTRAP_DBIAS_VAL 0
68 #define XTAL_32K_BOOTSTRAP_TIME_US 7
70 /* Delays for various clock sources to be enabled/switched.
71 * All values are in microseconds.
72 * TODO: some of these are excessive, and should be reduced.
74 #define DELAY_CPU_FREQ_SWITCH_TO_XTAL_WITH_150K 80
75 #define DELAY_CPU_FREQ_SWITCH_TO_XTAL_WITH_32K 160
76 #define DELAY_CPU_FREQ_SWITCH_TO_PLL 10
77 #define DELAY_PLL_DBIAS_RAISE 3
78 #define DELAY_PLL_ENABLE_WITH_150K 80
79 #define DELAY_PLL_ENABLE_WITH_32K 160
80 #define DELAY_FAST_CLK_SWITCH 3
81 #define DELAY_SLOW_CLK_SWITCH 300
82 #define DELAY_8M_ENABLE 50
84 /* Number of 8M/256 clock cycles to use for XTAL frequency estimation.
85 * 10 cycles will take approximately 300 microseconds.
87 #define XTAL_FREQ_EST_CYCLES 10
90 static void rtc_clk_32k_enable_internal(int dac, int dres, int dbias)
92 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
93 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG,
94 RTC_IO_X32P_RDE | RTC_IO_X32P_RUE | RTC_IO_X32N_RUE |
95 RTC_IO_X32N_RDE | RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
96 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DAC_XTAL_32K, dac);
97 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DRES_XTAL_32K, dres);
98 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, dbias);
99 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
102 void rtc_clk_32k_enable(bool enable)
105 rtc_clk_32k_enable_internal(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DBIAS_VAL);
107 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
111 void rtc_clk_32k_bootstrap()
113 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
114 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_RUE | RTC_IO_X32N_RDE);
115 ets_delay_us(XTAL_32K_BOOTSTRAP_TIME_US);
116 rtc_clk_32k_enable_internal(XTAL_32K_BOOTSTRAP_DAC_VAL,
117 XTAL_32K_BOOTSTRAP_DRES_VAL, XTAL_32K_BOOTSTRAP_DBIAS_VAL);
120 bool rtc_clk_32k_enabled()
122 return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K) != 0;
125 void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
128 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
129 /* no need to wait once enabled by software */
130 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1);
132 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
134 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
136 ets_delay_us(DELAY_8M_ENABLE);
138 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
139 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
143 bool rtc_clk_8m_enabled()
145 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
148 bool rtc_clk_8md256_enabled()
150 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
153 void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div)
155 REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD, enable ? 0 : 1);
156 REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0);
157 REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD, enable ? 0 : 1);
160 REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) != RTC_CNTL_SOC_CLK_SEL_PLL) {
161 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
165 uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1;
166 uint32_t is_rev0 = (GET_PERI_REG_BITS2(EFUSE_BLK0_RDATA3_REG, 1, 15) == 0);
170 sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0;
172 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM2, sdm2);
173 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM0, sdm0);
174 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM1, sdm1);
175 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
176 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, sdm_stop_val_2);
177 I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
180 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
181 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
182 I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
184 /* wait for calibration end */
185 while (!(I2C_READREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_CAL_END))) {
186 /* use ets_delay_us so the RTC bus doesn't get flooded */
192 void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
194 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
195 ets_delay_us(DELAY_SLOW_CLK_SWITCH);
198 rtc_slow_freq_t rtc_clk_slow_freq_get()
200 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
203 uint32_t rtc_clk_slow_freq_get_hz()
205 switch(rtc_clk_slow_freq_get()) {
206 case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
207 case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K;
208 case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256;
213 void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)
215 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq);
216 ets_delay_us(DELAY_FAST_CLK_SWITCH);
219 rtc_fast_freq_t rtc_clk_fast_freq_get()
221 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
224 void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_cpu_freq_t cpu_freq)
233 if (cpu_freq != RTC_CPU_FREQ_240M) {
234 /* Configure 320M PLL */
236 case RTC_XTAL_FREQ_40M:
244 case RTC_XTAL_FREQ_26M:
252 case RTC_XTAL_FREQ_24M:
269 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_320M);
270 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_320M);
272 /* Raise the voltage */
273 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V25);
274 ets_delay_us(DELAY_PLL_DBIAS_RAISE);
275 /* Configure 480M PLL */
277 case RTC_XTAL_FREQ_40M:
285 case RTC_XTAL_FREQ_26M:
293 case RTC_XTAL_FREQ_24M:
310 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_480M);
311 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_480M);
314 uint8_t i2c_bbpll_lref = (lref << 7) | (div10_8 << 4) | (div_ref);
315 uint8_t i2c_bbpll_div_7_0 = div7_0;
316 uint8_t i2c_bbpll_dcur = (bw << 6) | dcur;
317 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref);
318 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
319 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
320 uint32_t delay_pll_en = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ?
321 DELAY_PLL_ENABLE_WITH_150K : DELAY_PLL_ENABLE_WITH_32K;
322 ets_delay_us(delay_pll_en);
325 void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq)
327 rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
328 /* Switch CPU to XTAL frequency first */
329 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V10);
330 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
331 REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0);
332 ets_update_cpu_frequency(xtal_freq);
333 uint32_t delay_xtal_switch = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ?
334 DELAY_CPU_FREQ_SWITCH_TO_XTAL_WITH_150K : DELAY_CPU_FREQ_SWITCH_TO_XTAL_WITH_32K;
335 ets_delay_us(delay_xtal_switch);
336 DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
337 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
338 RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
339 RTC_CNTL_BBPLL_I2C_FORCE_PD);
340 rtc_clk_apb_freq_update(xtal_freq * MHZ);
342 /* is APLL under force power down? */
343 uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
345 /* then also power down the internal I2C bus */
346 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
348 /* now switch to the desired frequency */
349 if (cpu_freq == RTC_CPU_FREQ_XTAL) {
350 /* already at XTAL, nothing to do */
351 } else if (cpu_freq == RTC_CPU_FREQ_2M) {
352 /* set up divider to produce 2MHz from XTAL */
353 REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, (xtal_freq / 2) - 1);
354 ets_update_cpu_frequency(2);
355 rtc_clk_apb_freq_update(2 * MHZ);
356 /* lower the voltage */
357 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V00);
359 /* use PLL as clock source */
360 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
361 RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD |
362 RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
363 rtc_clk_bbpll_set(xtal_freq, cpu_freq);
364 if (cpu_freq == RTC_CPU_FREQ_80M) {
365 DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
366 ets_update_cpu_frequency(80);
367 } else if (cpu_freq == RTC_CPU_FREQ_160M) {
368 DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1);
369 ets_update_cpu_frequency(160);
370 } else if (cpu_freq == RTC_CPU_FREQ_240M) {
371 DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2);
372 ets_update_cpu_frequency(240);
374 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
375 ets_delay_us(DELAY_CPU_FREQ_SWITCH_TO_PLL);
376 rtc_clk_apb_freq_update(80 * MHZ);
380 rtc_cpu_freq_t rtc_clk_cpu_freq_get()
382 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
383 switch (soc_clk_sel) {
384 case RTC_CNTL_SOC_CLK_SEL_XTL: {
385 uint32_t pre_div = REG_GET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT);
387 return RTC_CPU_FREQ_XTAL;
388 } else if (pre_div == rtc_clk_xtal_freq_get() / 2 - 1) {
389 return RTC_CPU_FREQ_2M;
391 assert(false && "unsupported frequency");
395 case RTC_CNTL_SOC_CLK_SEL_PLL: {
396 uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
397 if (cpuperiod_sel == 0) {
398 return RTC_CPU_FREQ_80M;
399 } else if (cpuperiod_sel == 1) {
400 return RTC_CPU_FREQ_160M;
401 } else if (cpuperiod_sel == 2) {
402 return RTC_CPU_FREQ_240M;
404 assert(false && "unsupported frequency");
408 case RTC_CNTL_SOC_CLK_SEL_APLL:
409 case RTC_CNTL_SOC_CLK_SEL_8M:
411 assert(false && "unsupported frequency");
413 return RTC_CNTL_SOC_CLK_SEL_XTL;
416 uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq)
419 case RTC_CPU_FREQ_XTAL:
420 return ((uint32_t) rtc_clk_xtal_freq_get()) * MHZ;
421 case RTC_CPU_FREQ_2M:
423 case RTC_CPU_FREQ_80M:
425 case RTC_CPU_FREQ_160M:
427 case RTC_CPU_FREQ_240M:
430 assert(false && "invalid rtc_cpu_freq_t value");
435 /* Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in
436 * lower and upper 16-bit halves. These are the routines to work with such a
439 static bool clk_val_is_valid(uint32_t val) {
440 return (val & 0xffff) == ((val >> 16) & 0xffff) &&
445 static uint32_t reg_val_to_clk_val(uint32_t val) {
446 return val & UINT16_MAX;
449 static uint32_t clk_val_to_reg_val(uint32_t val) {
450 return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16);
453 rtc_xtal_freq_t rtc_clk_xtal_freq_get()
455 /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */
456 uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
457 if (!clk_val_is_valid(xtal_freq_reg)) {
458 SOC_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value: 0x%08x", xtal_freq_reg);
459 return RTC_XTAL_FREQ_AUTO;
461 return reg_val_to_clk_val(xtal_freq_reg);
464 void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
466 WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
469 static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate()
471 uint64_t cal_val = rtc_clk_cal_ratio(RTC_CAL_8MD256, XTAL_FREQ_EST_CYCLES);
472 /* cal_val contains period of 8M/256 clock in XTAL clock cycles
473 * (shifted by RTC_CLK_CAL_FRACT bits).
474 * Xtal frequency will be (cal_val * 8M / 256) / 2^19
476 uint32_t freq_mhz = (cal_val * (RTC_FAST_CLK_FREQ_APPROX / MHZ) / 256 ) >> RTC_CLK_CAL_FRACT;
477 /* Guess the XTAL type. For now, only 40 and 26MHz are supported.
481 return RTC_XTAL_FREQ_26M;
483 SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 26 MHz", freq_mhz);
484 return RTC_XTAL_FREQ_26M;
486 SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 40 MHz", freq_mhz);
487 return RTC_XTAL_FREQ_40M;
489 return RTC_XTAL_FREQ_40M;
491 SOC_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz);
492 return RTC_XTAL_FREQ_AUTO;
496 void rtc_clk_apb_freq_update(uint32_t apb_freq)
498 WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
501 uint32_t rtc_clk_apb_freq_get()
503 uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
504 // round to the nearest MHz
506 uint32_t remainder = freq_hz % MHZ;
507 return freq_hz - remainder;
511 void rtc_clk_init(rtc_clk_config_t cfg)
513 /* If we get a TG WDT system reset while running at 240MHz,
514 * DPORT_CPUPERIOD_SEL register will be reset to 0 resulting in 120MHz
515 * APB and CPU frequencies after reset. This will cause issues with XTAL
516 * frequency estimation, so we switch to XTAL frequency first.
518 * Ideally we would only do this if RTC_CNTL_SOC_CLK_SEL == PLL and
519 * PLL is configured for 480M, but it takes less time to switch to 40M and
520 * run the following code than querying the PLL does.
522 if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) == RTC_CNTL_SOC_CLK_SEL_PLL) {
523 rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL);
526 /* Set tuning parameters for 8M and 150k clocks.
527 * Note: this doesn't attempt to set the clocks to precise frequencies.
528 * Instead, we calibrate these clocks against XTAL frequency later, when necessary.
529 * - SCK_DCAP value controls tuning of 150k clock.
530 * The higher the value of DCAP is, the lower is the frequency.
531 * - CK8M_DFREQ value controls tuning of 8M clock.
532 * CLK_8M_DFREQ constant gives the best temperature characteristics.
534 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
535 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
537 /* Configure 8M clock division */
538 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, cfg.clk_8m_div);
540 /* Enable the internal bus used to configure PLLs */
541 SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
542 CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M);
544 /* Estimate XTAL frequency if requested */
545 rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
546 if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
547 if (clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) {
548 /* XTAL frequency has already been set, use existing value */
549 xtal_freq = rtc_clk_xtal_freq_get();
551 /* Not set yet, estimate XTAL frequency based on RTC_FAST_CLK */
552 xtal_freq = rtc_clk_xtal_freq_estimate();
553 if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
554 SOC_LOGW(TAG, "Can't estimate XTAL frequency, assuming 26MHz");
555 xtal_freq = RTC_XTAL_FREQ_26M;
559 rtc_clk_xtal_freq_update(xtal_freq);
560 rtc_clk_apb_freq_update(xtal_freq * MHZ);
561 /* Set CPU frequency */
562 rtc_clk_cpu_freq_set(cfg.cpu_freq);
564 /* Slow & fast clocks setup */
565 if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
566 rtc_clk_32k_enable(true);
568 if (cfg.fast_freq == RTC_FAST_FREQ_8M) {
569 bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256;
570 rtc_clk_8m_enable(true, need_8md256);
572 rtc_clk_fast_freq_set(cfg.fast_freq);
573 rtc_clk_slow_freq_set(cfg.slow_freq);
576 /* Name used in libphy.a:phy_chip_v7.o
577 * TODO: update the library to use rtc_clk_xtal_freq_get
579 rtc_xtal_freq_t rtc_get_xtal() __attribute__((alias("rtc_clk_xtal_freq_get")));