granicus.if.org Git - esp-idf/blob - components/soc/esp32/include/soc/soc.h

   1 // Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
   2 //
   3 // Licensed under the Apache License, Version 2.0 (the "License");
   4 // you may not use this file except in compliance with the License.
   5 // You may obtain a copy of the License at
   6 //
   7 //     http://www.apache.org/licenses/LICENSE-2.0
   8 //
   9 // Unless required by applicable law or agreed to in writing, software
  10 // distributed under the License is distributed on an "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12 // See the License for the specific language governing permissions and
  13 // limitations under the License.
  14
  15 #ifndef _ESP32_SOC_H_
  16 #define _ESP32_SOC_H_
  17
  18 #ifndef __ASSEMBLER__
  19 #include <stdint.h>
  20 #include "esp_assert.h"
  21 #endif
  22
  23 //Register Bits{{
  24 #define BIT31   0x80000000
  25 #define BIT30   0x40000000
  26 #define BIT29   0x20000000
  27 #define BIT28   0x10000000
  28 #define BIT27   0x08000000
  29 #define BIT26   0x04000000
  30 #define BIT25   0x02000000
  31 #define BIT24   0x01000000
  32 #define BIT23   0x00800000
  33 #define BIT22   0x00400000
  34 #define BIT21   0x00200000
  35 #define BIT20   0x00100000
  36 #define BIT19   0x00080000
  37 #define BIT18   0x00040000
  38 #define BIT17   0x00020000
  39 #define BIT16   0x00010000
  40 #define BIT15   0x00008000
  41 #define BIT14   0x00004000
  42 #define BIT13   0x00002000
  43 #define BIT12   0x00001000
  44 #define BIT11   0x00000800
  45 #define BIT10   0x00000400
  46 #define BIT9     0x00000200
  47 #define BIT8     0x00000100
  48 #define BIT7     0x00000080
  49 #define BIT6     0x00000040
  50 #define BIT5     0x00000020
  51 #define BIT4     0x00000010
  52 #define BIT3     0x00000008
  53 #define BIT2     0x00000004
  54 #define BIT1     0x00000002
  55 #define BIT0     0x00000001
  56 //}}
  57
  58 #define PRO_CPU_NUM (0)
  59 #define APP_CPU_NUM (1)
  60
  61 /* Overall memory map */
  62 #define SOC_IROM_LOW    0x400D0000
  63 #define SOC_IROM_HIGH   0x40400000
  64 #define SOC_DROM_LOW    0x3F400000
  65 #define SOC_DROM_HIGH   0x3F800000
  66 #define SOC_RTC_IRAM_LOW  0x400C0000
  67 #define SOC_RTC_IRAM_HIGH 0x400C2000
  68 #define SOC_RTC_DATA_LOW  0x50000000
  69 #define SOC_RTC_DATA_HIGH 0x50002000
  70
  71 #define DR_REG_DPORT_BASE                       0x3ff00000
  72 #define DR_REG_DPORT_END                        0x3ff00FFC
  73 #define DR_REG_RSA_BASE                         0x3ff02000
  74 #define DR_REG_SHA_BASE                         0x3ff03000
  75 #define DR_REG_UART_BASE                        0x3ff40000
  76 #define DR_REG_SPI1_BASE                        0x3ff42000
  77 #define DR_REG_SPI0_BASE                        0x3ff43000
  78 #define DR_REG_GPIO_BASE                        0x3ff44000
  79 #define DR_REG_GPIO_SD_BASE                     0x3ff44f00
  80 #define DR_REG_FE2_BASE                         0x3ff45000
  81 #define DR_REG_FE_BASE                          0x3ff46000
  82 #define DR_REG_FRC_TIMER_BASE                   0x3ff47000
  83 #define DR_REG_RTCCNTL_BASE                     0x3ff48000
  84 #define DR_REG_RTCIO_BASE                       0x3ff48400
  85 #define DR_REG_SENS_BASE                        0x3ff48800
  86 #define DR_REG_IO_MUX_BASE                      0x3ff49000
  87 #define DR_REG_RTCMEM0_BASE                     0x3ff61000
  88 #define DR_REG_RTCMEM1_BASE                     0x3ff62000
  89 #define DR_REG_RTCMEM2_BASE                     0x3ff63000
  90 #define DR_REG_SYSCON_BASE                      0x3ff66000
  91 #define DR_REG_HINF_BASE                        0x3ff4B000
  92 #define DR_REG_UHCI1_BASE                       0x3ff4C000
  93 #define DR_REG_I2S_BASE                         0x3ff4F000
  94 #define DR_REG_UART1_BASE                       0x3ff50000
  95 #define DR_REG_BT_BASE                          0x3ff51000
  96 #define DR_REG_I2C_EXT_BASE                     0x3ff53000
  97 #define DR_REG_UHCI0_BASE                       0x3ff54000
  98 #define DR_REG_SLCHOST_BASE                     0x3ff55000
  99 #define DR_REG_RMT_BASE                         0x3ff56000
 100 #define DR_REG_PCNT_BASE                        0x3ff57000
 101 #define DR_REG_SLC_BASE                         0x3ff58000
 102 #define DR_REG_LEDC_BASE                        0x3ff59000
 103 #define DR_REG_EFUSE_BASE                       0x3ff5A000
 104 #define DR_REG_SPI_ENCRYPT_BASE                 0x3ff5B000
 105 #define DR_REG_NRX_BASE                         0x3ff5CC00
 106 #define DR_REG_BB_BASE                          0x3ff5D000
 107 #define DR_REG_PWM_BASE                         0x3ff5E000
 108 #define DR_REG_TIMERGROUP0_BASE                 0x3ff5F000
 109 #define DR_REG_TIMERGROUP1_BASE                 0x3ff60000
 110 #define DR_REG_SPI2_BASE                        0x3ff64000
 111 #define DR_REG_SPI3_BASE                        0x3ff65000
 112 #define DR_REG_APB_CTRL_BASE                    0x3ff66000
 113 #define DR_REG_I2C1_EXT_BASE                    0x3ff67000
 114 #define DR_REG_SDMMC_BASE                       0x3ff68000
 115 #define DR_REG_EMAC_BASE                        0x3ff69000
 116 #define DR_REG_PWM1_BASE                        0x3ff6C000
 117 #define DR_REG_I2S1_BASE                        0x3ff6D000
 118 #define DR_REG_UART2_BASE                       0x3ff6E000
 119 #define DR_REG_PWM2_BASE                        0x3ff6F000
 120 #define DR_REG_PWM3_BASE                        0x3ff70000
 121 #define PERIPHS_SPI_ENCRYPT_BASEADDR            DR_REG_SPI_ENCRYPT_BASE
 122
 123 //Registers Operation {{
 124 #define ETS_UNCACHED_ADDR(addr) (addr)
 125 #define ETS_CACHED_ADDR(addr) (addr)
 126
 127 #ifndef __ASSEMBLER__
 128 #define BIT(nr)                 (1UL << (nr))
 129 #else
 130 #define BIT(nr)                 (1 << (nr))
 131 #endif
 132
 133 #ifndef __ASSEMBLER__
 134
 135 #define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
 136
 137 #if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM )
 138 #define ASSERT_IF_DPORT_REG(_r, OP)  TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
 139 #else
 140 #define ASSERT_IF_DPORT_REG(_r, OP)
 141 #endif
 142
 143 //write value to register
 144 #define REG_WRITE(_r, _v) ({                                                                                           \
 145             ASSERT_IF_DPORT_REG((_r), REG_WRITE);                                                                      \
 146             (*(volatile uint32_t *)(_r)) = (_v);                                                                       \
 147         })
 148
 149 //read value from register
 150 #define REG_READ(_r) ({                                                                                                \
 151             ASSERT_IF_DPORT_REG((_r), REG_READ);                                                                       \
 152             (*(volatile uint32_t *)(_r));                                                                              \
 153         })
 154
 155 //get bit or get bits from register
 156 #define REG_GET_BIT(_r, _b)  ({                                                                                        \
 157             ASSERT_IF_DPORT_REG((_r), REG_GET_BIT);                                                                    \
 158             (*(volatile uint32_t*)(_r) & (_b));                                                                        \
 159         })
 160
 161 //set bit or set bits to register
 162 #define REG_SET_BIT(_r, _b)  ({                                                                                        \
 163             ASSERT_IF_DPORT_REG((_r), REG_SET_BIT);                                                                    \
 164             (*(volatile uint32_t*)(_r) |= (_b));                                                                       \
 165         })
 166
 167 //clear bit or clear bits of register
 168 #define REG_CLR_BIT(_r, _b)  ({                                                                                        \
 169             ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT);                                                                    \
 170             (*(volatile uint32_t*)(_r) &= ~(_b));                                                                      \
 171         })
 172
 173 //set bits of register controlled by mask
 174 #define REG_SET_BITS(_r, _b, _m) ({                                                                                    \
 175             ASSERT_IF_DPORT_REG((_r), REG_SET_BITS);                                                                   \
 176             (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)));                         \
 177         })
 178
 179 //get field from register, uses field _S & _V to determine mask
 180 #define REG_GET_FIELD(_r, _f) ({                                                                                       \
 181             ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD);                                                                  \
 182             ((REG_READ(_r) >> (_f##_S)) & (_f##_V));                                                                   \
 183         })
 184
 185 //set field of a register from variable, uses field _S & _V to determine mask
 186 #define REG_SET_FIELD(_r, _f, _v) ({                                                                                   \
 187             ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD);                                                                  \
 188             (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))));                \
 189         })
 190
 191 //get field value from a variable, used when _f is not left shifted by _f##_S
 192 #define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
 193
 194 //get field value from a variable, used when _f is left shifted by _f##_S
 195 #define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
 196
 197 //set field value to a variable, used when _f is not left shifted by _f##_S
 198 #define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
 199
 200 //set field value to a variable, used when _f is left shifted by _f##_S
 201 #define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
 202
 203 //generate a value from a field value, used when _f is not left shifted by _f##_S
 204 #define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
 205
 206 //generate a value from a field value, used when _f is left shifted by _f##_S
 207 #define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
 208
 209 //read value from register
 210 #define READ_PERI_REG(addr) ({                                                                                         \
 211             ASSERT_IF_DPORT_REG((addr), READ_PERI_REG);                                                                \
 212             (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)));                                                         \
 213         })
 214
 215 //write value to register
 216 #define WRITE_PERI_REG(addr, val) ({                                                                                   \
 217             ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG);                                                               \
 218             (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val);                                       \
 219         })
 220
 221 //clear bits of register controlled by mask
 222 #define CLEAR_PERI_REG_MASK(reg, mask) ({                                                                              \
 223             ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK);                                                           \
 224             WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))));                                                     \
 225         })
 226
 227 //set bits of register controlled by mask
 228 #define SET_PERI_REG_MASK(reg, mask) ({                                                                                \
 229             ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK);                                                             \
 230             WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)));                                                        \
 231         })
 232
 233 //get bits of register controlled by mask
 234 #define GET_PERI_REG_MASK(reg, mask) ({                                                                                \
 235             ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK);                                                             \
 236             (READ_PERI_REG(reg) & (mask));                                                                             \
 237         })
 238
 239 //get bits of register controlled by highest bit and lowest bit
 240 #define GET_PERI_REG_BITS(reg, hipos,lowpos) ({                                                                        \
 241             ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS);                                                             \
 242             ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1));                                            \
 243         })
 244
 245 //set bits of register controlled by mask and shift
 246 #define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({                                                                  \
 247             ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS);                                                             \
 248             (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ));      \
 249         })
 250
 251 //get field of register
 252 #define GET_PERI_REG_BITS2(reg, mask,shift) ({                                                                         \
 253             ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2);                                                            \
 254             ((READ_PERI_REG(reg)>>(shift))&(mask));                                                                    \
 255         })
 256
 257 #endif /* !__ASSEMBLER__ */
 258 //}}
 259
 260 //Periheral Clock {{
 261 #define  APB_CLK_FREQ_ROM                            ( 26*1000000 )
 262 #define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
 263 #define  CPU_CLK_FREQ                                APB_CLK_FREQ
 264 #define  APB_CLK_FREQ                                ( 80*1000000 )       //unit: Hz
 265 #define  UART_CLK_FREQ                               APB_CLK_FREQ
 266 #define  WDT_CLK_FREQ                                APB_CLK_FREQ
 267 #define  TIMER_CLK_FREQ                              (80000000>>4) //80MHz divided by 16
 268 #define  SPI_CLK_DIV                                 4
 269 #define  TICKS_PER_US_ROM                            26              // CPU is 80MHz
 270 //}}
 271
 272 //Interrupt hardware source table
 273 //This table is decided by hardware, don't touch this.
 274 #define ETS_WIFI_MAC_INTR_SOURCE                0/**< interrupt of WiFi MAC, level*/
 275 #define ETS_WIFI_MAC_NMI_SOURCE                 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
 276 #define ETS_WIFI_BB_INTR_SOURCE                 2/**< interrupt of WiFi BB, level, we can do some calibartion*/
 277 #define ETS_BT_MAC_INTR_SOURCE                  3/**< will be cancelled*/
 278 #define ETS_BT_BB_INTR_SOURCE                   4/**< interrupt of BT BB, level*/
 279 #define ETS_BT_BB_NMI_SOURCE                    5/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
 280 #define ETS_RWBT_INTR_SOURCE                    6/**< interrupt of RWBT, level*/
 281 #define ETS_RWBLE_INTR_SOURCE                   7/**< interrupt of RWBLE, level*/
 282 #define ETS_RWBT_NMI_SOURCE                     8/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
 283 #define ETS_RWBLE_NMI_SOURCE                    9/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
 284 #define ETS_SLC0_INTR_SOURCE                    10/**< interrupt of SLC0, level*/
 285 #define ETS_SLC1_INTR_SOURCE                    11/**< interrupt of SLC1, level*/
 286 #define ETS_UHCI0_INTR_SOURCE                   12/**< interrupt of UHCI0, level*/
 287 #define ETS_UHCI1_INTR_SOURCE                   13/**< interrupt of UHCI1, level*/
 288 #define ETS_TG0_T0_LEVEL_INTR_SOURCE            14/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/
 289 #define ETS_TG0_T1_LEVEL_INTR_SOURCE            15/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/
 290 #define ETS_TG0_WDT_LEVEL_INTR_SOURCE           16/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/
 291 #define ETS_TG0_LACT_LEVEL_INTR_SOURCE          17/**< interrupt of TIMER_GROUP0, LACT, level*/
 292 #define ETS_TG1_T0_LEVEL_INTR_SOURCE            18/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/
 293 #define ETS_TG1_T1_LEVEL_INTR_SOURCE            19/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/
 294 #define ETS_TG1_WDT_LEVEL_INTR_SOURCE           20/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
 295 #define ETS_TG1_LACT_LEVEL_INTR_SOURCE          21/**< interrupt of TIMER_GROUP1, LACT, level*/
 296 #define ETS_GPIO_INTR_SOURCE                    22/**< interrupt of GPIO, level*/
 297 #define ETS_GPIO_NMI_SOURCE                     23/**< interrupt of GPIO, NMI*/
 298 #define ETS_FROM_CPU_INTR0_SOURCE               24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
 299 #define ETS_FROM_CPU_INTR1_SOURCE               25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
 300 #define ETS_FROM_CPU_INTR2_SOURCE               26/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
 301 #define ETS_FROM_CPU_INTR3_SOURCE               27/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
 302 #define ETS_SPI0_INTR_SOURCE                    28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/
 303 #define ETS_SPI1_INTR_SOURCE                    29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
 304 #define ETS_SPI2_INTR_SOURCE                    30/**< interrupt of SPI2, level*/
 305 #define ETS_SPI3_INTR_SOURCE                    31/**< interrupt of SPI3, level*/
 306 #define ETS_I2S0_INTR_SOURCE                    32/**< interrupt of I2S0, level*/
 307 #define ETS_I2S1_INTR_SOURCE                    33/**< interrupt of I2S1, level*/
 308 #define ETS_UART0_INTR_SOURCE                   34/**< interrupt of UART0, level*/
 309 #define ETS_UART1_INTR_SOURCE                   35/**< interrupt of UART1, level*/
 310 #define ETS_UART2_INTR_SOURCE                   36/**< interrupt of UART2, level*/
 311 #define ETS_SDIO_HOST_INTR_SOURCE               37/**< interrupt of SD/SDIO/MMC HOST, level*/
 312 #define ETS_ETH_MAC_INTR_SOURCE                 38/**< interrupt of ethernet mac, level*/
 313 #define ETS_PWM0_INTR_SOURCE                    39/**< interrupt of PWM0, level, Reserved*/
 314 #define ETS_PWM1_INTR_SOURCE                    40/**< interrupt of PWM1, level, Reserved*/
 315 #define ETS_PWM2_INTR_SOURCE                    41/**< interrupt of PWM2, level*/
 316 #define ETS_PWM3_INTR_SOURCE                    42/**< interruot of PWM3, level*/
 317 #define ETS_LEDC_INTR_SOURCE                    43/**< interrupt of LED PWM, level*/
 318 #define ETS_EFUSE_INTR_SOURCE                   44/**< interrupt of efuse, level, not likely to use*/
 319 #define ETS_CAN_INTR_SOURCE                     45/**< interrupt of can, level*/
 320 #define ETS_RTC_CORE_INTR_SOURCE                46/**< interrupt of rtc core, level, include rtc watchdog*/
 321 #define ETS_RMT_INTR_SOURCE                     47/**< interrupt of remote controller, level*/
 322 #define ETS_PCNT_INTR_SOURCE                    48/**< interrupt of pluse count, level*/
 323 #define ETS_I2C_EXT0_INTR_SOURCE                49/**< interrupt of I2C controller1, level*/
 324 #define ETS_I2C_EXT1_INTR_SOURCE                50/**< interrupt of I2C controller0, level*/
 325 #define ETS_RSA_INTR_SOURCE                     51/**< interrupt of RSA accelerator, level*/
 326 #define ETS_SPI1_DMA_INTR_SOURCE                52/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/
 327 #define ETS_SPI2_DMA_INTR_SOURCE                53/**< interrupt of SPI2 DMA, level*/
 328 #define ETS_SPI3_DMA_INTR_SOURCE                54/**< interrupt of SPI3 DMA, level*/
 329 #define ETS_WDT_INTR_SOURCE                     55/**< will be cancelled*/
 330 #define ETS_TIMER1_INTR_SOURCE                  56/**< will be cancelled*/
 331 #define ETS_TIMER2_INTR_SOURCE                  57/**< will be cancelled*/
 332 #define ETS_TG0_T0_EDGE_INTR_SOURCE             58/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/
 333 #define ETS_TG0_T1_EDGE_INTR_SOURCE             59/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/
 334 #define ETS_TG0_WDT_EDGE_INTR_SOURCE            60/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
 335 #define ETS_TG0_LACT_EDGE_INTR_SOURCE           61/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
 336 #define ETS_TG1_T0_EDGE_INTR_SOURCE             62/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/
 337 #define ETS_TG1_T1_EDGE_INTR_SOURCE             63/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
 338 #define ETS_TG1_WDT_EDGE_INTR_SOURCE            64/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
 339 #define ETS_TG1_LACT_EDGE_INTR_SOURCE           65/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
 340 #define ETS_MMU_IA_INTR_SOURCE                  66/**< interrupt of MMU Invalid Access, LEVEL*/
 341 #define ETS_MPU_IA_INTR_SOURCE                  67/**< interrupt of MPU Invalid Access, LEVEL*/
 342 #define ETS_CACHE_IA_INTR_SOURCE                68/**< interrupt of Cache Invalied Access, LEVEL*/
 343
 344 //interrupt cpu using table, Please see the core-isa.h
 345 /*************************************************************************************************************
 346  *      Intr num                Level           Type                    PRO CPU usage           APP CPU uasge
 347  *      0                       1               extern level            WMAC                    Reserved
 348  *      1                       1               extern level            BT/BLE Host HCI DMA     BT/BLE Host HCI DMA
 349  *      2                       1               extern level
 350  *      3                       1               extern level
 351  *      4                       1               extern level            WBB
 352  *      5                       1               extern level            BT/BLE Controller       BT/BLE Controller
 353  *      6                       1               timer                   FreeRTOS Tick(L1)       FreeRTOS Tick(L1)
 354  *      7                       1               software                BT/BLE VHCI             BT/BLE VHCI
 355  *      8                       1               extern level            BT/BLE BB(RX/TX)        BT/BLE BB(RX/TX)
 356  *      9                       1               extern level
 357  *      10                      1               extern edge             Internal Timer
 358  *      11                      3               profiling
 359  *      12                      1               extern level
 360  *      13                      1               extern level
 361  *      14                      7               nmi                     Reserved                Reserved
 362  *      15                      3               timer                   FreeRTOS Tick(L3)       FreeRTOS Tick(L3)
 363  *      16                      5               timer
 364  *      17                      1               extern level
 365  *      18                      1               extern level
 366  *      19                      2               extern level
 367  *      20                      2               extern level
 368  *      21                      2               extern level
 369  *      22                      3               extern edge             FRC1 timer
 370  *      23                      3               extern level
 371  *      24                      4               extern level            TG1_WDT
 372  *      25                      4               extern level            CACHEERR
 373  *      26                      5               extern level            Reserved                Reserved
 374  *      27                      3               extern level            Reserved                Reserved
 375  *      28                      4               extern edge
 376  *      29                      3               software                Reserved                Reserved
 377  *      30                      4               extern edge             Reserved                Reserved
 378  *      31                      5               extern level            DPORT ACCESS            DPORT ACCESS
 379  *************************************************************************************************************
 380  */
 381
 382 //CPU0 Interrupt number reserved, not touch this.
 383 #define ETS_WMAC_INUM                           0
 384 #define ETS_BT_HOST_INUM                        1
 385 #define ETS_WBB_INUM                            4
 386 #define ETS_TG0_T1_INUM                         10 /**< use edge interrupt*/
 387 #define ETS_FRC1_INUM                           22
 388 #define ETS_T1_WDT_INUM                         24
 389 #define ETS_CACHEERR_INUM                       25
 390 #define ETS_DPORT_INUM                          31
 391
 392 //CPU0 Interrupt number used in ROM, should be cancelled in SDK
 393 #define ETS_SLC_INUM                            1
 394 #define ETS_UART0_INUM                          5
 395 #define ETS_UART1_INUM                          5
 396 //Other interrupt number should be managed by the user
 397
 398 //Invalid interrupt for number interrupt matrix
 399 #define ETS_INVALID_INUM                        6
 400
 401 #endif /* _ESP32_SOC_H_ */