1 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
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12 // See the License for the specific language governing permissions and
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27 * @brief Low-level RTC power, clock, and sleep functions.
29 * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
30 * RTC_CNTL peripheral handles many functions:
31 * - enables/disables clocks and power to various parts of the chip; this is
32 * done using direct register access (forcing power up or power down) or by
33 * allowing state machines to control power and clocks automatically
34 * - handles sleep and wakeup functions
35 * - maintains a 48-bit counter which can be used for timekeeping
37 * These functions are not thread safe, and should not be viewed as high level
38 * APIs. For example, while this file provides a function which can switch
39 * CPU frequency, this function is on its own is not sufficient to implement
40 * frequency switching in ESP-IDF context: some coordination with RTOS,
41 * peripheral drivers, and WiFi/BT stacks is also required.
43 * These functions will normally not be used in applications directly.
44 * ESP-IDF provides, or will provide, drivers and other facilities to use
45 * RTC subsystem functionality.
47 * The functions are loosely split into the following groups:
48 * - rtc_clk: clock switching, calibration
49 * - rtc_time: reading RTC counter, conversion between counter values and time
50 * - rtc_sleep: entry into sleep modes
51 * - rtc_init: initialization
56 * @brief Possible main XTAL frequency values.
58 * Enum values should be equal to frequency in MHz.
61 RTC_XTAL_FREQ_AUTO = 0, //!< Automatic XTAL frequency detection
62 RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
63 RTC_XTAL_FREQ_26M = 26, //!< 26 MHz XTAL
64 RTC_XTAL_FREQ_24M = 24, //!< 24 MHz XTAL
68 * @brief CPU frequency values
71 RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency
72 RTC_CPU_FREQ_80M = 1, //!< 80 MHz
73 RTC_CPU_FREQ_160M = 2, //!< 160 MHz
74 RTC_CPU_FREQ_240M = 3, //!< 240 MHz
75 RTC_CPU_FREQ_2M = 4, //!< 2 MHz
79 * @brief RTC SLOW_CLK frequency values
82 RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator
83 RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL
84 RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256
88 * @brief RTC FAST_CLK frequency values
91 RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4
92 RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator
95 /* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */
96 #define RTC_FAST_CLK_FREQ_APPROX 8500000
99 * @brief Clock source to be calibrated using rtc_clk_cal function
102 RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
103 RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
104 RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL
108 * Initialization parameters for rtc_clk_init
111 rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
112 rtc_cpu_freq_t cpu_freq : 3; //!< CPU frequency to set
113 rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set
114 rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set
115 uint32_t clk_8m_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
116 uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
117 uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
121 * Default initializer for rtc_clk_config_t
123 #define RTC_CLK_CONFIG_DEFAULT() { \
124 .xtal_freq = RTC_XTAL_FREQ_AUTO, \
125 .cpu_freq = RTC_CPU_FREQ_80M, \
126 .fast_freq = RTC_FAST_FREQ_8M, \
127 .slow_freq = RTC_SLOW_FREQ_RTC, \
129 .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
130 .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
134 * Initialize clocks and set CPU frequency
136 * If cfg.xtal_freq is set to RTC_XTAL_FREQ_AUTO, this function will attempt
137 * to auto detect XTAL frequency. Auto detection is performed by comparing
138 * XTAL frequency with the frequency of internal 8MHz oscillator. Note that at
139 * high temperatures the frequency of the internal 8MHz oscillator may drift
140 * enough for auto detection to be unreliable.
141 * Auto detection code will attempt to distinguish between 26MHz and 40MHz
142 * crystals. 24 MHz crystals are not supported by auto detection code.
143 * If XTAL frequency can not be auto detected, this 26MHz frequency will be used.
145 * @param cfg clock configuration as rtc_clk_config_t
147 void rtc_clk_init(rtc_clk_config_t cfg);
150 * @brief Get main XTAL frequency
152 * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
153 * rtc_clk_init function, or if the value was RTC_XTAL_FREQ_AUTO, the detected
156 * @return XTAL frequency, one of rtc_xtal_freq_t
158 rtc_xtal_freq_t rtc_clk_xtal_freq_get();
161 * @brief Update XTAL frequency
163 * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
166 * @param xtal_freq New frequency value
168 void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
171 * @brief Enable or disable 32 kHz XTAL oscillator
172 * @param en true to enable, false to disable
174 void rtc_clk_32k_enable(bool en);
177 * @brief Get the state of 32k XTAL oscillator
178 * @return true if 32k XTAL oscillator has been enabled
180 bool rtc_clk_32k_enabled();
183 * @brief Enable 32k oscillator, configuring it for fast startup time.
184 * Note: to achieve higher frequency stability, rtc_clk_32k_enable function
185 * must be called one the 32k XTAL oscillator has started up. This function
186 * will initially disable the 32k XTAL oscillator, so it should not be called
187 * when the system is using 32k XTAL as RTC_SLOW_CLK.
189 * @param cycle Number of 32kHz cycles to bootstrap external crystal.
190 * If 0, no square wave will be used to bootstrap crystal oscillation.
192 void rtc_clk_32k_bootstrap(uint32_t cycle);
195 * @brief Enable or disable 8 MHz internal oscillator
197 * Output from 8 MHz internal oscillator is passed into a configurable
198 * divider, which by default divides the input clock frequency by 256.
199 * Output of the divider may be used as RTC_SLOW_CLK source.
200 * Output of the divider is referred to in register descriptions and code as
201 * 8md256 or simply d256. Divider values other than 256 may be configured, but
202 * this facility is not currently needed, so is not exposed in the code.
204 * When 8MHz/256 divided output is not needed, the divider should be disabled
205 * to reduce power consumption.
207 * @param clk_8m_en true to enable 8MHz generator
208 * @param d256_en true to enable /256 divider
210 void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
213 * @brief Get the state of 8 MHz internal oscillator
214 * @return true if the oscillator is enabled
216 bool rtc_clk_8m_enabled();
219 * @brief Get the state of /256 divider which is applied to 8MHz clock
220 * @return true if the divided output is enabled
222 bool rtc_clk_8md256_enabled();
225 * @brief Enable or disable APLL
227 * Output frequency is given by the formula:
228 * apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2)
230 * The dividend in this expression should be in the range of 240 - 600 MHz.
232 * In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0.
234 * @param enable true to enable, false to disable
235 * @param sdm0 frequency adjustment parameter, 0..255
236 * @param sdm1 frequency adjustment parameter, 0..255
237 * @param sdm2 frequency adjustment parameter, 0..63
238 * @param o_div frequency divider, 0..31
240 void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1,
241 uint32_t sdm2, uint32_t o_div);
244 * @brief Select source for RTC_SLOW_CLK
245 * @param slow_freq clock source (one of rtc_slow_freq_t values)
247 void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq);
250 * @brief Get the RTC_SLOW_CLK source
251 * @return currently selected clock source (one of rtc_slow_freq_t values)
253 rtc_slow_freq_t rtc_clk_slow_freq_get();
256 * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
258 * - if RTC_SLOW_FREQ_RTC is selected, returns ~150000
259 * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768
260 * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000
262 * rtc_clk_cal function can be used to get more precise value by comparing
263 * RTC_SLOW_CLK frequency to the frequency of main XTAL.
265 * @return RTC_SLOW_CLK frequency, in Hz
267 uint32_t rtc_clk_slow_freq_get_hz();
270 * @brief Select source for RTC_FAST_CLK
271 * @param fast_freq clock source (one of rtc_fast_freq_t values)
273 void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq);
276 * @brief Get the RTC_FAST_CLK source
277 * @return currently selected clock source (one of rtc_fast_freq_t values)
279 rtc_fast_freq_t rtc_clk_fast_freq_get();
282 * @brief Switch CPU frequency
284 * If a PLL-derived frequency is requested (80, 160, 240 MHz), this function
285 * will enable the PLL. Otherwise, PLL will be disabled.
286 * Note: this function is not optimized for switching speed. It may take several
287 * hundred microseconds to perform frequency switch.
289 * @param cpu_freq new CPU frequency
291 void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq);
294 * @brief Switch CPU frequency
296 * This is a faster version of rtc_clk_cpu_freq_set, which can handle some of
297 * the frequency switch paths (XTAL -> PLL, PLL -> XTAL).
298 * When switching from PLL to XTAL, PLL is not disabled (unlike rtc_clk_cpu_freq_set).
299 * When switching back from XTAL to PLL, only the same PLL can be used.
300 * Therefore it is not possible to switch 240 -> XTAL -> (80 or 160) using this
303 * For unsupported cases, this function falls back to rtc_clk_cpu_freq_set.
305 * Unlike rtc_clk_cpu_freq_set, this function relies on static data, so it is
306 * less safe to use it e.g. from a panic handler (when memory might be corrupted).
308 * @param cpu_freq new CPU frequency
310 void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq);
313 * @brief Get the currently selected CPU frequency
315 * Although CPU can be clocked by APLL and RTC 8M sources, such support is not
316 * exposed through this library. As such, this function will not return
317 * meaningful values when these clock sources are configured (e.g. using direct
318 * access to clock selection registers). In debug builds, it will assert; in
319 * release builds, it will return RTC_CPU_FREQ_XTAL.
321 * @return CPU frequency (one of rtc_cpu_freq_t values)
323 rtc_cpu_freq_t rtc_clk_cpu_freq_get();
326 * @brief Get corresponding frequency value for rtc_cpu_freq_t enum value
327 * @param cpu_freq CPU frequency, on of rtc_cpu_freq_t values
328 * @return CPU frequency, in HZ
330 uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq);
333 * @brief Get rtc_cpu_freq_t enum value for given CPU frequency
334 * @param cpu_freq_mhz CPU frequency, one of 80, 160, 240, 2, and XTAL frequency
335 * @param[out] out_val output, rtc_cpu_freq_t value corresponding to the frequency
336 * @return true if the given frequency value matches one of enum values
338 bool rtc_clk_cpu_freq_from_mhz(int cpu_freq_mhz, rtc_cpu_freq_t* out_val);
341 * @brief Store new APB frequency value into RTC_APB_FREQ_REG
343 * This function doesn't change any hardware clocks.
345 * Functions which perform frequency switching and change APB frequency call
346 * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG
347 * (one of RTC general purpose retention registers). This should not normally
348 * be called from application code.
350 * @param apb_freq new APB frequency, in Hz
352 void rtc_clk_apb_freq_update(uint32_t apb_freq);
355 * @brief Get the current stored APB frequency.
356 * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
358 uint32_t rtc_clk_apb_freq_get();
360 #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
363 * @brief Measure RTC slow clock's period, based on main XTAL frequency
365 * This function will time out and return 0 if the time for the given number
366 * of cycles to be counted exceeds the expected time twice. This may happen if
367 * 32k XTAL is being calibrated, but the oscillator has not started up (due to
368 * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
370 * @param cal_clk clock to be measured
371 * @param slow_clk_cycles number of slow clock cycles to average
372 * @return average slow clock period in microseconds, Q13.19 fixed point format,
373 * or 0 if calibration has timed out
375 uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
378 * @brief Measure ratio between XTAL frequency and RTC slow clock frequency
379 * @param cal_clk slow clock to be measured
380 * @param slow_clk_cycles number of slow clock cycles to average
381 * @return average ratio between XTAL frequency and slow clock frequency,
382 * Q13.19 fixed point format, or 0 if calibration has timed out.
384 uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
387 * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
388 * @param time_in_us Time interval in microseconds
389 * @param slow_clk_period Period of slow clock in microseconds, Q13.19
390 * fixed point format (as returned by rtc_slowck_cali).
391 * @return number of slow clock cycles
393 uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period);
396 * @brief Convert time interval from RTC_SLOW_CLK to microseconds
397 * @param time_in_us Time interval in RTC_SLOW_CLK cycles
398 * @param slow_clk_period Period of slow clock in microseconds, Q13.19
399 * fixed point format (as returned by rtc_slowck_cali).
400 * @return time interval in microseconds
402 uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
405 * @brief Get current value of RTC counter
407 * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK
408 * cycles. Counter value is not writable by software. The value is not adjusted
409 * when switching to a different RTC_SLOW_CLK source.
411 * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
413 * @return current value of RTC counter
415 uint64_t rtc_time_get();
418 * @brief Busy loop until next RTC_SLOW_CLK cycle
420 * This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
421 * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
422 * one RTC_SLOW_CLK cycle later.
424 void rtc_clk_wait_for_slow_cycle();
427 * @brief sleep configuration for rtc_sleep_init function
430 uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory)
431 uint32_t rtc_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (RTC memory)
432 uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
433 uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory
434 uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
435 uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
436 uint32_t wifi_pd_en : 1; //!< power down WiFi
437 uint32_t rom_mem_pd_en : 1; //!< power down main RAM and ROM
438 uint32_t deep_slp : 1; //!< power down digital domain
439 uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
440 uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode
441 uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode
442 uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode
443 uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode
444 uint32_t lslp_meminf_pd : 1; //!< remove all peripheral force power up flags
445 uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
446 uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
447 } rtc_sleep_config_t;
450 * Default initializer for rtc_sleep_config_t
452 * This initializer sets all fields to "reasonable" values (e.g. suggested for
453 * production use) based on a combination of RTC_SLEEP_PD_x flags.
455 * @param RTC_SLEEP_PD_x flags combined using bitwise OR
457 #define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
458 .lslp_mem_inf_fpu = 0, \
459 .rtc_mem_inf_fpu = 0, \
460 .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
461 .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \
462 .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
463 .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
465 .rom_mem_pd_en = 0, \
466 .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
467 .wdt_flashboot_mod_en = 0, \
468 .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \
469 .dig_dbias_slp = RTC_CNTL_DBIAS_0V90, \
470 .rtc_dbias_wak = RTC_CNTL_DBIAS_0V90, \
471 .rtc_dbias_slp = RTC_CNTL_DBIAS_0V90, \
472 .lslp_meminf_pd = 1, \
473 .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
474 .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1 \
477 #define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain)
478 #define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals
479 #define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory
480 #define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory
481 #define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
482 #define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator
483 #define RTC_SLEEP_PD_XTAL BIT(6) //!< Power down main XTAL
486 * @brief Prepare the chip to enter sleep mode
488 * This function configures various power control state machines to handle
489 * entry into light sleep or deep sleep mode, switches APB and CPU clock source
490 * (usually to XTAL), and sets bias voltages for digital and RTC power domains.
492 * This function does not actually enter sleep mode; this is done using
493 * rtc_sleep_start function. Software may do some other actions between
494 * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure
496 * @param cfg sleep mode configuration
498 void rtc_sleep_init(rtc_sleep_config_t cfg);
502 * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source
503 * @param t value of RTC counter at which wakeup from sleep will happen;
504 * only the lower 48 bits are used
506 void rtc_sleep_set_wakeup_time(uint64_t t);
509 #define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup
510 #define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup
511 #define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup (light sleep only)
512 #define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup
513 #define RTC_SDIO_TRIG_EN BIT(4) //!< SDIO wakeup (light sleep only)
514 #define RTC_MAC_TRIG_EN BIT(5) //!< MAC wakeup (light sleep only)
515 #define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only)
516 #define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only)
517 #define RTC_TOUCH_TRIG_EN BIT(8) //!< Touch wakeup
518 #define RTC_ULP_TRIG_EN BIT(9) //!< ULP wakeup
519 #define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only)
522 * @brief Enter deep or light sleep mode
524 * This function enters the sleep mode previously configured using rtc_sleep_init
525 * function. Before entering sleep, software should configure wake up sources
526 * appropriately (set up GPIO wakeup registers, timer wakeup registers,
529 * If deep sleep mode was configured using rtc_sleep_init, and sleep is not
530 * rejected by hardware (based on reject_opt flags), this function never returns.
531 * When the chip wakes up from deep sleep, CPU is reset and execution starts
532 * from ROM bootloader.
534 * If light sleep mode was configured using rtc_sleep_init, this function
535 * returns on wakeup, or if sleep is rejected by hardware.
537 * @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags
539 * @param reject_opt bit mask of sleep reject reasons:
540 * - RTC_CNTL_GPIO_REJECT_EN
541 * - RTC_CNTL_SDIO_REJECT_EN
542 * These flags are used to prevent entering sleep when e.g.
543 * an external host is communicating via SDIO slave
544 * @return non-zero if sleep was rejected by hardware
546 uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
549 * RTC power and clock control initialization settings
552 uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
553 uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
554 uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
555 uint32_t clkctl_init : 1; //!< Perform clock control related initialization
556 uint32_t pwrctl_init : 1; //!< Perform power control related initialization
557 uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST
561 * Default initializer of rtc_config_t.
563 * This initializer sets all fields to "reasonable" values (e.g. suggested for
566 #define RTC_CONFIG_DEFAULT() {\
567 .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \
568 .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \
569 .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
572 .rtc_dboost_fpd = 1 \
576 * Initialize RTC clock and power control related functions
577 * @param cfg configuration options as rtc_config_t
579 void rtc_init(rtc_config_t cfg);
582 * Structure describing vddsdio configuration
585 uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
586 uint32_t enable : 1; //!< Enable VDDSDIO regulator
587 uint32_t tieh : 1; //!< Select VDDSDIO voltage: 1 — 1.8V, 0 — 3.3V
588 uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator
589 uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator
590 uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator
591 } rtc_vddsdio_config_t;
594 * Get current VDDSDIO configuration
595 * If VDDSDIO configuration is overridden by RTC, get values from RTC
596 * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE
597 * Otherwise, use default values and the level of MTDI bootstrapping pin.
598 * @return currently used VDDSDIO configuration
600 rtc_vddsdio_config_t rtc_vddsdio_get_config();
603 * Set new VDDSDIO configuration using RTC registers.
604 * If config.force == 1, this overrides configuration done using bootstrapping
607 * @param config new VDDSDIO configuration
609 void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);