1 // Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
17 #include "esp_system.h"
20 #include "esp_wifi_internal.h"
22 #include "sdkconfig.h"
23 #include "rom/efuse.h"
24 #include "rom/cache.h"
26 #include "soc/dport_reg.h"
27 #include "soc/gpio_reg.h"
28 #include "soc/efuse_reg.h"
29 #include "soc/rtc_cntl_reg.h"
30 #include "soc/timer_group_reg.h"
31 #include "soc/timer_group_struct.h"
34 #include "freertos/FreeRTOS.h"
35 #include "freertos/task.h"
36 #include "freertos/xtensa_api.h"
37 #include "esp_heap_caps.h"
39 static const char* TAG = "system_api";
41 static uint8_t base_mac_addr[6] = { 0 };
43 #define SHUTDOWN_HANDLERS_NO 2
44 static shutdown_handler_t shutdown_handlers[SHUTDOWN_HANDLERS_NO];
50 esp_err_t esp_base_mac_addr_set(uint8_t *mac)
53 ESP_LOGE(TAG, "Base MAC address is NULL");
57 memcpy(base_mac_addr, mac, 6);
62 esp_err_t esp_base_mac_addr_get(uint8_t *mac)
64 uint8_t null_mac[6] = {0};
66 if (memcmp(base_mac_addr, null_mac, 6) == 0) {
67 ESP_LOGI(TAG, "Base MAC address is not set, read default base MAC address from BLK0 of EFUSE");
68 return ESP_ERR_INVALID_MAC;
71 memcpy(mac, base_mac_addr, 6);
76 esp_err_t esp_efuse_mac_get_custom(uint8_t *mac)
83 uint8_t version = REG_READ(EFUSE_BLK3_RDATA5_REG) >> 24;
86 ESP_LOGE(TAG, "Base MAC address from BLK3 of EFUSE version error, version = %d", version);
87 return ESP_ERR_INVALID_VERSION;
90 mac_low = REG_READ(EFUSE_BLK3_RDATA1_REG);
91 mac_high = REG_READ(EFUSE_BLK3_RDATA0_REG);
93 mac[0] = mac_high >> 8;
94 mac[1] = mac_high >> 16;
95 mac[2] = mac_high >> 24;
97 mac[4] = mac_low >> 8;
98 mac[5] = mac_low >> 16;
100 efuse_crc = mac_high;
102 calc_crc = esp_crc8(mac, 6);
104 if (efuse_crc != calc_crc) {
105 ESP_LOGE(TAG, "Base MAC address from BLK3 of EFUSE CRC error, efuse_crc = 0x%02x; calc_crc = 0x%02x", efuse_crc, calc_crc);
106 return ESP_ERR_INVALID_CRC;
111 esp_err_t esp_efuse_mac_get_default(uint8_t* mac)
118 mac_low = REG_READ(EFUSE_BLK0_RDATA1_REG);
119 mac_high = REG_READ(EFUSE_BLK0_RDATA2_REG);
121 mac[0] = mac_high >> 8;
123 mac[2] = mac_low >> 24;
124 mac[3] = mac_low >> 16;
125 mac[4] = mac_low >> 8;
128 efuse_crc = mac_high >> 16;
130 calc_crc = esp_crc8(mac, 6);
132 if (efuse_crc != calc_crc) {
133 // Small range of MAC addresses are accepted even if CRC is invalid.
134 // These addresses are reserved for Espressif internal use.
135 if ((mac_high & 0xFFFF) == 0x18fe) {
136 if ((mac_low >= 0x346a85c7) && (mac_low <= 0x346a85f8)) {
140 ESP_LOGE(TAG, "Base MAC address from BLK0 of EFUSE CRC error, efuse_crc = 0x%02x; calc_crc = 0x%02x", efuse_crc, calc_crc);
147 esp_err_t system_efuse_read_mac(uint8_t *mac) __attribute__((alias("esp_efuse_mac_get_default")));
148 esp_err_t esp_efuse_read_mac(uint8_t *mac) __attribute__((alias("esp_efuse_mac_get_default")));
150 esp_err_t esp_derive_mac(uint8_t* local_mac, const uint8_t* universal_mac)
154 if (local_mac == NULL || universal_mac == NULL) {
155 ESP_LOGE(TAG, "mac address param is NULL");
156 return ESP_ERR_INVALID_ARG;
159 memcpy(local_mac, universal_mac, 6);
160 for (idx = 0; idx < 64; idx++) {
161 local_mac[0] = universal_mac[0] | 0x02;
162 local_mac[0] ^= idx << 2;
164 if (memcmp(local_mac, universal_mac, 6)) {
172 esp_err_t esp_read_mac(uint8_t* mac, esp_mac_type_t type)
174 uint8_t efuse_mac[6];
177 ESP_LOGE(TAG, "mac address param is NULL");
178 return ESP_ERR_INVALID_ARG;
181 if (type < ESP_MAC_WIFI_STA || type > ESP_MAC_ETH) {
182 ESP_LOGE(TAG, "mac type is incorrect");
183 return ESP_ERR_INVALID_ARG;
186 _Static_assert(UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR \
187 || UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR, \
188 "incorrect NUM_MAC_ADDRESS_FROM_EFUSE value");
190 if (esp_base_mac_addr_get(efuse_mac) != ESP_OK) {
191 esp_efuse_mac_get_default(efuse_mac);
195 case ESP_MAC_WIFI_STA:
196 memcpy(mac, efuse_mac, 6);
198 case ESP_MAC_WIFI_SOFTAP:
199 if (UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR) {
200 memcpy(mac, efuse_mac, 6);
203 else if (UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR) {
204 esp_derive_mac(mac, efuse_mac);
208 memcpy(mac, efuse_mac, 6);
209 if (UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR) {
212 else if (UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR) {
217 if (UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR) {
218 memcpy(mac, efuse_mac, 6);
221 else if (UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR) {
223 esp_derive_mac(mac, efuse_mac);
227 ESP_LOGW(TAG, "incorrect mac type");
234 esp_err_t esp_register_shutdown_handler(shutdown_handler_t handler)
237 for (i = 0; i < SHUTDOWN_HANDLERS_NO; i++) {
238 if (shutdown_handlers[i] == NULL) {
239 shutdown_handlers[i] = handler;
246 void esp_restart_noos() __attribute__ ((noreturn));
248 void IRAM_ATTR esp_restart(void)
251 for (i = 0; i < SHUTDOWN_HANDLERS_NO; i++) {
252 if (shutdown_handlers[i]) {
253 shutdown_handlers[i]();
257 // Disable scheduler on this core.
263 /* "inner" restart function for after RTOS, interrupts & anything else on this
264 * core are already stopped. Stalls other core, resets hardware,
267 void IRAM_ATTR esp_restart_noos()
269 // Disable interrupts
270 xt_ints_off(0xFFFFFFFF);
272 // Enable RTC watchdog for 1 second
273 REG_WRITE(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
274 REG_WRITE(RTC_CNTL_WDTCONFIG0_REG,
275 RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M |
276 (RTC_WDT_STG_SEL_RESET_SYSTEM << RTC_CNTL_WDT_STG0_S) |
277 (RTC_WDT_STG_SEL_RESET_RTC << RTC_CNTL_WDT_STG1_S) |
278 (1 << RTC_CNTL_WDT_SYS_RESET_LENGTH_S) |
279 (1 << RTC_CNTL_WDT_CPU_RESET_LENGTH_S) );
280 REG_WRITE(RTC_CNTL_WDTCONFIG1_REG, rtc_clk_slow_freq_get_hz() * 1);
282 // Reset and stall the other CPU.
283 // CPU must be reset before stalling, in case it was running a s32c1i
284 // instruction. This would cause memory pool to be locked by arbiter
285 // to the stalled CPU, preventing current CPU from accessing this pool.
286 const uint32_t core_id = xPortGetCoreID();
287 const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
288 esp_cpu_reset(other_core_id);
289 esp_cpu_stall(other_core_id);
291 // Other core is now stalled, can access DPORT registers directly
292 esp_dport_access_int_abort();
294 // Disable TG0/TG1 watchdogs
295 TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
296 TIMERG0.wdt_config0.en = 0;
297 TIMERG0.wdt_wprotect=0;
298 TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
299 TIMERG1.wdt_config0.en = 0;
300 TIMERG1.wdt_wprotect=0;
302 // Flush any data left in UART FIFOs
303 uart_tx_wait_idle(0);
304 uart_tx_wait_idle(1);
305 uart_tx_wait_idle(2);
308 Cache_Read_Disable(0);
309 Cache_Read_Disable(1);
311 // 2nd stage bootloader reconfigures SPI flash signals.
312 // Reset them to the defaults expected by ROM.
313 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
314 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
315 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
316 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
317 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
318 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
320 // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
321 DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
322 DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
323 DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
324 DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
325 DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
326 DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
328 // Reset timer/spi/uart
329 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
330 DPORT_TIMERS_RST | DPORT_SPI_RST_1 | DPORT_UART_RST);
331 DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
333 // Set CPU back to XTAL source, no PLL, same as hard reset
334 rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL);
336 // Clear entry point for APP CPU
337 DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0);
341 // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
345 // Running on APP CPU: need to reset PRO CPU and unstall it,
346 // then reset APP CPU
356 void system_restart(void) __attribute__((alias("esp_restart")));
358 uint32_t esp_get_free_heap_size( void )
360 return heap_caps_get_free_size( MALLOC_CAP_DEFAULT );
363 uint32_t esp_get_minimum_free_heap_size( void )
365 return heap_caps_get_minimum_free_size( MALLOC_CAP_DEFAULT );
368 uint32_t system_get_free_heap_size(void) __attribute__((alias("esp_get_free_heap_size")));
370 const char* system_get_sdk_version(void)
375 const char* esp_get_idf_version(void)
380 static void get_chip_info_esp32(esp_chip_info_t* out_info)
382 out_info->model = CHIP_ESP32;
383 uint32_t reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
384 memset(out_info, 0, sizeof(*out_info));
385 if ((reg & EFUSE_RD_CHIP_VER_REV1_M) != 0) {
386 out_info->revision = 1;
388 if ((reg & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) {
393 out_info->features = CHIP_FEATURE_WIFI_BGN;
394 if ((reg & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) {
395 out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE;
397 int package = (reg & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S;
398 if (package == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
399 package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
400 package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
401 out_info->features |= CHIP_FEATURE_EMB_FLASH;
405 void esp_chip_info(esp_chip_info_t* out_info)
407 // Only ESP32 is supported now, in the future call one of the
408 // chip-specific functions based on sdkconfig choice
409 return get_chip_info_esp32(out_info);