2 Abstraction layer for spi-ram. For now, it's no more than a stub for the spiram_psram functions, but if
3 we add more types of external RAM memory, this can be made into a more intelligent dispatcher.
6 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
8 // Licensed under the Apache License, Version 2.0 (the "License");
9 // you may not use this file except in compliance with the License.
10 // You may obtain a copy of the License at
12 // http://www.apache.org/licenses/LICENSE-2.0
14 // Unless required by applicable law or agreed to in writing, software
15 // distributed under the License is distributed on an "AS IS" BASIS,
16 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
17 // See the License for the specific language governing permissions and
18 // limitations under the License.
22 #include <sys/param.h>
24 #include "sdkconfig.h"
27 #include "esp_spiram.h"
28 #include "spiram_psram.h"
30 #include "freertos/FreeRTOS.h"
31 #include "freertos/xtensa_api.h"
33 #include "esp_heap_caps_init.h"
34 #include "soc/soc_memory_layout.h"
35 #include "soc/dport_reg.h"
36 #include "rom/cache.h"
38 #if CONFIG_FREERTOS_UNICORE
39 #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
41 #if CONFIG_MEMMAP_SPIRAM_CACHE_EVENODD
42 #define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD
44 #define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
48 #if CONFIG_SPIRAM_SUPPORT
50 static const char* TAG = "spiram";
52 #if CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_40M
53 #define PSRAM_SPEED PSRAM_CACHE_F40M_S40M
54 #elif CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
55 #define PSRAM_SPEED PSRAM_CACHE_F80M_S40M
56 #elif CONFIG_SPIRAM_SPEED_80M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
57 #define PSRAM_SPEED PSRAM_CACHE_F80M_S80M
59 #error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!"
63 static bool spiram_inited=false;
67 Simple RAM test. Writes a word every 32 bytes. Takes about a second to complete for 4MiB. Returns
68 true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been
69 initialized (in a two-core system) or after the heap allocator has taken ownership of the memory.
71 bool esp_spiram_test()
73 volatile int *spiram=(volatile int*)SOC_EXTRAM_DATA_LOW;
75 size_t s=CONFIG_SPIRAM_SIZE;
78 for (p=0; p<(s/sizeof(int)); p+=8) {
79 spiram[p]=p^0xAAAAAAAA;
81 for (p=0; p<(s/sizeof(int)); p+=8) {
82 if (spiram[p]!=(p^0xAAAAAAAA)) {
84 if (errct==1) initial_err=p*4;
88 ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, s/32, initial_err+SOC_EXTRAM_DATA_LOW);
91 ESP_EARLY_LOGI(TAG, "SPI SRAM memory test OK");
96 void IRAM_ATTR esp_spiram_init_cache()
98 //Enable external RAM in MMU
99 cache_sram_mmu_set( 0, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
100 //Flush and enable icache for APP CPU
101 #if !CONFIG_FREERTOS_UNICORE
102 DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);
103 cache_sram_mmu_set( 1, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
107 esp_spiram_volt_t esp_spiram_get_chip_volt()
109 if (!spiram_inited) {
110 ESP_LOGE(TAG, "SPI RAM not initialized");
111 return ESP_SPIRAM_VOLT_INVALID;
113 psram_volt_t volt = psram_get_volt();
116 return ESP_SPIRAM_VOLT_1V8;
118 return ESP_SPIRAM_VOLT_3V3;
120 return ESP_SPIRAM_VOLT_INVALID;
124 esp_spiram_size_t esp_spiram_get_chip_size()
126 if (!spiram_inited) {
127 ESP_LOGE(TAG, "SPI RAM not initialized");
128 return ESP_SPIRAM_SIZE_INVALID;
130 psram_size_t psram_size = psram_get_size();
131 switch (psram_size) {
132 case PSRAM_SIZE_32MBITS:
133 return ESP_SPIRAM_SIZE_32MBITS;
134 case PSRAM_SIZE_64MBITS:
135 return ESP_SPIRAM_SIZE_64MBITS;
137 return ESP_SPIRAM_SIZE_INVALID;
141 esp_err_t esp_spiram_init()
144 r = psram_enable(PSRAM_SPEED, PSRAM_MODE);
146 #if CONFIG_SPIRAM_IGNORE_NOTFOUND
147 ESP_EARLY_LOGE(TAG, "SPI RAM enabled but initialization failed. Bailing out.");
152 ESP_EARLY_LOGI(TAG, "SPI RAM mode: %s", PSRAM_SPEED == PSRAM_CACHE_F40M_S40M ? "flash 40m sram 40m" : \
153 PSRAM_SPEED == PSRAM_CACHE_F80M_S40M ? "flash 80m sram 40m" : \
154 PSRAM_SPEED == PSRAM_CACHE_F80M_S80M ? "flash 80m sram 80m" : "ERROR");
155 ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in %s mode.", \
156 (PSRAM_MODE==PSRAM_VADDR_MODE_EVENODD)?"even/odd (2-core)": \
157 (PSRAM_MODE==PSRAM_VADDR_MODE_LOWHIGH)?"low/high (2-core)": \
158 (PSRAM_MODE==PSRAM_VADDR_MODE_NORMAL)?"normal (1-core)":"ERROR");
164 esp_err_t esp_spiram_add_to_heapalloc()
166 ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", CONFIG_SPIRAM_SIZE/1024);
167 //Add entire external RAM region to heap allocator. Heap allocator knows the capabilities of this type of memory, so there's
168 //no need to explicitly specify them.
169 return heap_caps_add_region((intptr_t)SOC_EXTRAM_DATA_LOW, (intptr_t)SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE-1);
173 static uint8_t *dma_heap;
175 esp_err_t esp_spiram_reserve_dma_pool(size_t size) {
176 ESP_EARLY_LOGI(TAG, "Reserving pool of %dK of internal memory for DMA/internal allocations", size/1024);
177 /* Pool may be allocated in multiple non-contiguous chunks, depending on available RAM */
179 size_t next_size = heap_caps_get_largest_free_block(MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
180 next_size = MIN(next_size, size);
182 ESP_EARLY_LOGD(TAG, "Allocating block of size %d bytes", next_size);
183 dma_heap = heap_caps_malloc(next_size, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
184 if (!dma_heap || next_size == 0) {
185 return ESP_ERR_NO_MEM;
188 uint32_t caps[] = { MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT };
189 esp_err_t e = heap_caps_add_region_with_caps(caps, (intptr_t) dma_heap, (intptr_t) dma_heap+next_size-1);
198 size_t esp_spiram_get_size()
200 return CONFIG_SPIRAM_SIZE;
204 Before flushing the cache, if psram is enabled as a memory-mapped thing, we need to write back the data in the cache to the psram first,
205 otherwise it will get lost. For now, we just read 64/128K of random PSRAM memory to do this.
207 void IRAM_ATTR esp_spiram_writeback_cache()
211 volatile uint8_t *psram=(volatile uint8_t*)SOC_EXTRAM_DATA_LOW;
212 int cache_was_disabled=0;
214 if (!spiram_inited) return;
216 //We need cache enabled for this to work. Re-enable it if needed; make sure we
217 //disable it again on exit as well.
218 if (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE)==0) {
219 cache_was_disabled|=(1<<0);
220 DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);
222 #ifndef CONFIG_FREERTOS_UNICORE
223 if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE)==0) {
224 cache_was_disabled|=(1<<1);
225 DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
229 #if CONFIG_FREERTOS_UNICORE
230 for (x=0; x<1024*64; x+=32) {
235 Note: this assumes the amount of external RAM is >2M. If it is 2M or less, what this code does is undefined. If
236 we ever support external RAM chips of 2M or smaller, this may need adjusting.
238 for (x=0; x<1024*64; x+=32) {
240 i+=psram[x+(1024*1024*2)+(1024*64)]; //address picked to also clear cache of app cpu in low/high mode
244 if (cache_was_disabled&(1<<0)) {
245 while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) ;
246 DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
248 #ifndef CONFIG_FREERTOS_UNICORE
249 if (cache_was_disabled&(1<<1)) {
250 while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1);
251 DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);