2 Abstraction layer for spi-ram. For now, it's no more than a stub for the spiram_psram functions, but if
3 we add more types of external RAM memory, this can be made into a more intelligent dispatcher.
6 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
8 // Licensed under the Apache License, Version 2.0 (the "License");
9 // you may not use this file except in compliance with the License.
10 // You may obtain a copy of the License at
12 // http://www.apache.org/licenses/LICENSE-2.0
14 // Unless required by applicable law or agreed to in writing, software
15 // distributed under the License is distributed on an "AS IS" BASIS,
16 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
17 // See the License for the specific language governing permissions and
18 // limitations under the License.
23 #include "sdkconfig.h"
26 #include "spiram_psram.h"
28 #include "freertos/FreeRTOS.h"
29 #include "freertos/xtensa_api.h"
31 #include "esp_heap_caps_init.h"
32 #include "soc/soc_memory_layout.h"
33 #include "soc/dport_reg.h"
34 #include "rom/cache.h"
36 #if CONFIG_FREERTOS_UNICORE
37 #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
39 #if CONFIG_MEMMAP_SPIRAM_CACHE_EVENODD
40 #define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD
42 #define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
46 #if CONFIG_SPIRAM_SUPPORT
48 static const char* TAG = "spiram";
50 #if CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_40M
51 #define PSRAM_SPEED PSRAM_CACHE_F40M_S40M
52 #elif CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
53 #define PSRAM_SPEED PSRAM_CACHE_F80M_S40M
54 #elif CONFIG_SPIRAM_SPEED_80M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
55 #define PSRAM_SPEED PSRAM_CACHE_F80M_S80M
57 #error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!"
61 static bool spiram_inited=false;
65 Simple RAM test. Writes a word every 32 bytes. Takes about a second to complete for 4MiB. Returns
66 true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been
67 initialized (in a two-core system) or after the heap allocator has taken ownership of the memory.
69 bool esp_spiram_test()
71 volatile int *spiram=(volatile int*)SOC_EXTRAM_DATA_LOW;
73 size_t s=CONFIG_SPIRAM_SIZE;
76 for (p=0; p<(s/sizeof(int)); p+=8) {
77 spiram[p]=p^0xAAAAAAAA;
79 for (p=0; p<(s/sizeof(int)); p+=8) {
80 if (spiram[p]!=(p^0xAAAAAAAA)) {
82 if (errct==1) initial_err=p*4;
86 ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, s/32, initial_err+SOC_EXTRAM_DATA_LOW);
89 ESP_EARLY_LOGI(TAG, "SPI SRAM memory test OK");
94 void IRAM_ATTR esp_spiram_init_cache()
96 //Enable external RAM in MMU
97 cache_sram_mmu_set( 0, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
98 //Flush and enable icache for APP CPU
99 #if !CONFIG_FREERTOS_UNICORE
100 DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);
101 cache_sram_mmu_set( 1, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
106 esp_err_t esp_spiram_init()
109 r = psram_enable(PSRAM_SPEED, PSRAM_MODE);
111 ESP_EARLY_LOGE(TAG, "SPI RAM enabled but initialization failed. Bailing out.");
115 ESP_EARLY_LOGI(TAG, "SPI RAM mode: %s", PSRAM_SPEED == PSRAM_CACHE_F40M_S40M ? "flash 40m sram 40m" : \
116 PSRAM_SPEED == PSRAM_CACHE_F80M_S40M ? "flash 80m sram 40m" : \
117 PSRAM_SPEED == PSRAM_CACHE_F80M_S80M ? "flash 80m sram 80m" : "ERROR");
118 ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in %s mode.", \
119 (PSRAM_MODE==PSRAM_VADDR_MODE_EVENODD)?"even/odd (2-core)": \
120 (PSRAM_MODE==PSRAM_VADDR_MODE_LOWHIGH)?"low/high (2-core)": \
121 (PSRAM_MODE==PSRAM_VADDR_MODE_NORMAL)?"normal (1-core)":"ERROR");
127 esp_err_t esp_spiram_add_to_heapalloc()
129 ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", CONFIG_SPIRAM_SIZE/1024);
130 //Add entire external RAM region to heap allocator. Heap allocator knows the capabilities of this type of memory, so there's
131 //no need to explicitly specify them.
132 return heap_caps_add_region((intptr_t)SOC_EXTRAM_DATA_LOW, (intptr_t)SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE-1);
136 static uint8_t *dma_heap;
138 esp_err_t esp_spiram_reserve_dma_pool(size_t size) {
139 if (size==0) return ESP_OK; //no-op
140 ESP_EARLY_LOGI(TAG, "Reserving pool of %dK of internal memory for DMA/internal allocations", size/1024);
141 dma_heap=heap_caps_malloc(size, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
142 if (!dma_heap) return ESP_ERR_NO_MEM;
143 uint32_t caps[]={MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT};
144 return heap_caps_add_region_with_caps(caps, (intptr_t) dma_heap, (intptr_t) dma_heap+size-1);
147 size_t esp_spiram_get_size()
149 return CONFIG_SPIRAM_SIZE;
153 Before flushing the cache, if psram is enabled as a memory-mapped thing, we need to write back the data in the cache to the psram first,
154 otherwise it will get lost. For now, we just read 64/128K of random PSRAM memory to do this.
156 void IRAM_ATTR esp_spiram_writeback_cache()
160 volatile uint8_t *psram=(volatile uint8_t*)SOC_EXTRAM_DATA_LOW;
161 int cache_was_disabled=0;
163 if (!spiram_inited) return;
165 //We need cache enabled for this to work. Re-enable it if needed; make sure we
166 //disable it again on exit as well.
167 if (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE)==0) {
168 cache_was_disabled|=(1<<0);
169 DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);
171 #ifndef CONFIG_FREERTOS_UNICORE
172 if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE)==0) {
173 cache_was_disabled|=(1<<1);
174 DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
178 #if CONFIG_FREERTOS_UNICORE
179 for (x=0; x<1024*64; x+=32) {
184 Note: this assumes the amount of external RAM is >2M. If it is 2M or less, what this code does is undefined. If
185 we ever support external RAM chips of 2M or smaller, this may need adjusting.
187 for (x=0; x<1024*64; x+=32) {
189 i+=psram[x+(1024*1024*2)+(1024*64)]; //address picked to also clear cache of app cpu in low/high mode
193 if (cache_was_disabled&(1<<0)) {
194 while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) ;
195 DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
197 #ifndef CONFIG_FREERTOS_UNICORE
198 if (cache_was_disabled&(1<<1)) {
199 while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1);
200 DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);