1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
18 #include "esp_deep_sleep.h"
20 #include "rom/cache.h"
24 #include "soc/rtc_cntl_reg.h"
25 #include "soc/dport_reg.h"
26 #include "driver/rtc_io.h"
27 #include "freertos/FreeRTOS.h"
28 #include "freertos/task.h"
30 #include "sdkconfig.h"
33 * Internal structure which holds all requested deep sleep parameters
36 esp_deep_sleep_pd_option_t pd_options[ESP_PD_DOMAIN_MAX];
37 uint64_t sleep_duration;
38 uint32_t wakeup_triggers : 11;
39 uint32_t ext1_trigger_mode : 1;
40 uint32_t ext1_rtc_gpio_mask : 18;
41 uint32_t ext0_trigger_level : 1;
42 uint32_t ext0_rtc_gpio_num : 5;
43 } deep_sleep_config_t;
45 static deep_sleep_config_t s_config = {
46 .pd_options = { ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO },
50 /* Updating RTC_MEMORY_CRC_REG register via set_rtc_memory_crc()
51 is not thread-safe. */
52 static _lock_t lock_rtc_memory_crc;
54 static const char* TAG = "deepsleep";
56 static uint32_t get_power_down_flags();
57 static void ext0_wakeup_prepare();
58 static void ext1_wakeup_prepare();
60 /* Wake from deep sleep stub
61 See esp_deepsleep.h esp_wake_deep_sleep() comments for details.
63 esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void)
65 _lock_acquire(&lock_rtc_memory_crc);
66 uint32_t stored_crc = REG_READ(RTC_MEMORY_CRC_REG);
68 uint32_t calc_crc = REG_READ(RTC_MEMORY_CRC_REG);
69 REG_WRITE(RTC_MEMORY_CRC_REG, stored_crc);
70 _lock_release(&lock_rtc_memory_crc);
72 if(stored_crc == calc_crc) {
73 return (esp_deep_sleep_wake_stub_fn_t)REG_READ(RTC_ENTRY_ADDR_REG);
79 void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub)
81 _lock_acquire(&lock_rtc_memory_crc);
82 REG_WRITE(RTC_ENTRY_ADDR_REG, (uint32_t)new_stub);
84 _lock_release(&lock_rtc_memory_crc);
87 void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void) {
88 /* Clear MMU for CPU 0 */
89 REG_SET_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MMU_IA_CLR);
90 REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MMU_IA_CLR);
91 #if CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY > 0
92 // ROM code has not started yet, so we need to set delay factor
93 // used by ets_delay_us first.
94 ets_update_cpu_frequency_rom(ets_get_detected_xtal_freq() / 1000000);
95 // This delay is configured in menuconfig, it can be used to give
96 // the flash chip some time to become ready.
97 ets_delay_us(CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY);
101 void __attribute__((weak, alias("esp_default_wake_deep_sleep"))) esp_wake_deep_sleep(void);
103 void esp_deep_sleep(uint64_t time_in_us)
105 esp_deep_sleep_enable_timer_wakeup(time_in_us);
106 esp_deep_sleep_start();
109 void IRAM_ATTR esp_deep_sleep_start()
111 // Decide which power domains can be powered down
112 uint32_t pd_flags = get_power_down_flags();
114 // Configure pins for external wakeup
115 if (s_config.wakeup_triggers & EXT_EVENT0_TRIG_EN) {
116 ext0_wakeup_prepare();
118 if (s_config.wakeup_triggers & EXT_EVENT1_TRIG_EN) {
119 ext1_wakeup_prepare();
121 // TODO: move timer wakeup configuration into a similar function
122 // once rtc_sleep is opensourced.
124 // Flush UARTs so that output is not lost due to APB frequency change
125 uart_tx_wait_idle(0);
126 uart_tx_wait_idle(1);
127 uart_tx_wait_idle(2);
129 if (esp_get_deep_sleep_wake_stub() == NULL) {
130 esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep);
133 rtc_set_cpu_freq(CPU_XTAL);
134 uint32_t cycle_h = 0;
135 uint32_t cycle_l = 0;
136 // For timer wakeup, calibrate clock source against main XTAL
137 // This is hardcoded to use 150kHz internal oscillator for now
138 if (s_config.sleep_duration > 0) {
139 uint32_t period = rtc_slowck_cali(CALI_RTC_MUX, 128);
140 rtc_usec2rtc(s_config.sleep_duration >> 32, s_config.sleep_duration & UINT32_MAX,
141 period, &cycle_h, &cycle_l);
144 rtc_slp_prep_lite(pd_flags, 0);
145 rtc_sleep(cycle_h, cycle_l, s_config.wakeup_triggers, 0);
146 // Because RTC is in a slower clock domain than the CPU, it
147 // can take several CPU cycles for the sleep mode to start.
153 void system_deep_sleep(uint64_t) __attribute__((alias("esp_deep_sleep")));
155 esp_err_t esp_deep_sleep_enable_ulp_wakeup()
157 #ifdef CONFIG_ULP_COPROC_ENABLED
158 s_config.wakeup_triggers |= RTC_SAR_TRIG_EN;
161 return ESP_ERR_INVALID_STATE;
165 esp_err_t esp_deep_sleep_enable_timer_wakeup(uint64_t time_in_us)
167 s_config.wakeup_triggers |= RTC_TIMER_EXPIRE_EN;
168 s_config.sleep_duration = time_in_us;
172 esp_err_t esp_deep_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
174 if (level < 0 || level > 1) {
175 return ESP_ERR_INVALID_ARG;
177 if (!RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
178 return ESP_ERR_INVALID_ARG;
180 s_config.ext0_rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num;
181 s_config.ext0_trigger_level = level;
182 s_config.wakeup_triggers |= RTC_EXT_EVENT0_TRIG_EN;
186 static void ext0_wakeup_prepare()
188 int rtc_gpio_num = s_config.ext0_rtc_gpio_num;
189 // Set GPIO to be used for wakeup
190 REG_SET_FIELD(RTC_IO_EXT_WAKEUP0_REG, RTC_IO_EXT_WAKEUP0_SEL, rtc_gpio_num);
191 // Set level which will trigger wakeup
192 SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
193 s_config.ext0_trigger_level, RTC_CNTL_EXT_WAKEUP0_LV_S);
194 // Find GPIO descriptor in the rtc_gpio_desc table and configure the pad
195 for (size_t gpio_num = 0; gpio_num < GPIO_PIN_COUNT; ++gpio_num) {
196 const rtc_gpio_desc_t* desc = &rtc_gpio_desc[gpio_num];
197 if (desc->rtc_num == rtc_gpio_num) {
198 REG_SET_BIT(desc->reg, desc->mux);
199 SET_PERI_REG_BITS(desc->reg, 0x3, 0, desc->func);
200 REG_SET_BIT(desc->reg, desc->slpsel);
201 REG_SET_BIT(desc->reg, desc->slpie);
207 esp_err_t esp_deep_sleep_enable_ext1_wakeup(uint64_t mask, esp_ext1_wakeup_mode_t mode)
209 if (mode > ESP_EXT1_WAKEUP_ANY_HIGH) {
210 return ESP_ERR_INVALID_ARG;
212 // Translate bit map of GPIO numbers into the bit map of RTC IO numbers
213 uint32_t rtc_gpio_mask = 0;
214 for (int gpio = 0; mask; ++gpio, mask >>= 1) {
215 if ((mask & 1) == 0) {
218 if (!RTC_GPIO_IS_VALID_GPIO(gpio)) {
219 ESP_LOGE(TAG, "Not an RTC IO: GPIO%d", gpio);
220 return ESP_ERR_INVALID_ARG;
222 rtc_gpio_mask |= BIT(rtc_gpio_desc[gpio].rtc_num);
224 s_config.ext1_rtc_gpio_mask = rtc_gpio_mask;
225 s_config.ext1_trigger_mode = mode;
226 s_config.wakeup_triggers |= RTC_EXT_EVENT1_TRIG_EN;
230 static void ext1_wakeup_prepare()
232 // Configure all RTC IOs selected as ext1 wakeup inputs
233 uint32_t rtc_gpio_mask = s_config.ext1_rtc_gpio_mask;
234 for (int gpio = 0; gpio < GPIO_PIN_COUNT && rtc_gpio_mask != 0; ++gpio) {
235 int rtc_pin = rtc_gpio_desc[gpio].rtc_num;
236 if ((rtc_gpio_mask & BIT(rtc_pin)) == 0) {
239 const rtc_gpio_desc_t* desc = &rtc_gpio_desc[gpio];
241 REG_SET_BIT(desc->reg, desc->mux);
242 SET_PERI_REG_BITS(desc->reg, 0x3, 0, desc->func);
243 // Pad configuration depends on RTC_PERIPH state in sleep mode
244 if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_ON) {
245 // set input enable in sleep mode
246 REG_SET_BIT(desc->reg, desc->slpie);
247 // allow sleep status signal to control IE/SLPIE mux
248 REG_SET_BIT(desc->reg, desc->slpsel);
250 // RTC_PERIPH will be disabled, so need to enable input and
251 // lock pad configuration. Pullups/pulldowns also need to be disabled.
252 REG_SET_BIT(desc->reg, desc->ie);
253 REG_CLR_BIT(desc->reg, desc->pulldown);
254 REG_CLR_BIT(desc->reg, desc->pullup);
255 REG_SET_BIT(RTC_CNTL_HOLD_FORCE_REG, desc->hold);
257 // Keep track of pins which are processed to bail out early
258 rtc_gpio_mask &= ~BIT(rtc_pin);
260 // Clear state from previous wakeup
261 REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
262 // Set pins to be used for wakeup
263 REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, s_config.ext1_rtc_gpio_mask);
264 // Set logic function (any low, all high)
265 SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
266 s_config.ext1_trigger_mode, RTC_CNTL_EXT_WAKEUP1_LV_S);
269 uint64_t esp_deep_sleep_get_ext1_wakeup_status()
271 int wakeup_reason = REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE);
272 if (wakeup_reason != RTC_EXT_EVENT1_TRIG) {
275 uint32_t status = REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS);
276 // Translate bit map of RTC IO numbers into the bit map of GPIO numbers
277 uint64_t gpio_mask = 0;
278 for (int gpio = 0; gpio < GPIO_PIN_COUNT; ++gpio) {
279 if (!RTC_GPIO_IS_VALID_GPIO(gpio)) {
282 int rtc_pin = rtc_gpio_desc[gpio].rtc_num;
283 if ((status & BIT(rtc_pin)) == 0) {
286 gpio_mask |= BIT(gpio);
291 esp_err_t esp_deep_sleep_pd_config(esp_deep_sleep_pd_domain_t domain,
292 esp_deep_sleep_pd_option_t option)
294 if (domain >= ESP_PD_DOMAIN_MAX || option > ESP_PD_OPTION_AUTO) {
295 return ESP_ERR_INVALID_ARG;
297 s_config.pd_options[domain] = option;
301 static uint32_t get_power_down_flags()
303 // Where needed, convert AUTO options to ON. Later interpret AUTO as OFF.
305 // RTC_SLOW_MEM is needed only for the ULP.
306 // If RTC_SLOW_MEM is Auto, and ULP wakeup isn't enabled, power down RTC_SLOW_MEM.
307 if (s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] == ESP_PD_OPTION_AUTO) {
308 if (s_config.wakeup_triggers & RTC_SAR_TRIG_EN) {
309 s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] = ESP_PD_OPTION_ON;
313 // RTC_FAST_MEM is needed for deep sleep stub.
314 // If RTC_FAST_MEM is Auto, keep it powered on, so that deep sleep stub
316 // In the new chip revision, deep sleep stub will be optional,
317 // and this can be changed.
318 if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] == ESP_PD_OPTION_AUTO) {
319 s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] = ESP_PD_OPTION_ON;
322 // RTC_PERIPH is needed for EXT0 wakeup and for ULP.
323 // If RTC_PERIPH is auto, and both EXT0 and ULP aren't enabled,
324 // power down RTC_PERIPH.
325 if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_AUTO) {
326 if (s_config.wakeup_triggers &
327 (RTC_SAR_TRIG_EN | RTC_EXT_EVENT0_TRIG_EN)) {
328 s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON;
332 const char* option_str[] = {"OFF", "ON", "AUTO(OFF)" /* Auto works as OFF */};
333 ESP_LOGD(TAG, "RTC_PERIPH: %s, RTC_SLOW_MEM: %s, RTC_FAST_MEM: %s",
334 option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH]],
335 option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM]],
336 option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM]]);
338 // Prepare flags based on the selected options
339 uint32_t pd_flags = DEEP_SLEEP_PD_NORMAL;
340 if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] != ESP_PD_OPTION_ON) {
341 pd_flags |= DEEP_SLEEP_PD_RTC_FAST_MEM;
343 if (s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] != ESP_PD_OPTION_ON) {
344 pd_flags |= DEEP_SLEEP_PD_RTC_SLOW_MEM;
346 if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) {
347 pd_flags |= DEEP_SLEEP_PD_RTC_PERIPH;