1 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
21 #include "rom/ets_sys.h"
24 #include "rom/cache.h"
28 #include "soc/dport_reg.h"
29 #include "soc/io_mux_reg.h"
30 #include "soc/rtc_cntl_reg.h"
31 #include "soc/timer_group_reg.h"
33 #include "driver/rtc_io.h"
35 #include "freertos/FreeRTOS.h"
36 #include "freertos/task.h"
37 #include "freertos/semphr.h"
38 #include "freertos/queue.h"
39 #include "freertos/portmacro.h"
41 #include "tcpip_adapter.h"
43 #include "esp_heap_caps_init.h"
44 #include "sdkconfig.h"
45 #include "esp_system.h"
46 #include "esp_spi_flash.h"
47 #include "nvs_flash.h"
48 #include "esp_event.h"
49 #include "esp_spi_flash.h"
51 #include "esp_crosscore_int.h"
52 #include "esp_dport_access.h"
54 #include "esp_vfs_dev.h"
55 #include "esp_newlib.h"
56 #include "esp_brownout.h"
57 #include "esp_int_wdt.h"
58 #include "esp_task_wdt.h"
59 #include "esp_phy_init.h"
60 #include "esp_cache_err_int.h"
61 #include "esp_coexist.h"
62 #include "esp_panic.h"
63 #include "esp_core_dump.h"
64 #include "esp_app_trace.h"
65 #include "esp_efuse.h"
66 #include "esp_spiram.h"
68 #include "esp_timer.h"
71 #define STRINGIFY(s) STRINGIFY2(s)
72 #define STRINGIFY2(s) #s
74 void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default"))) __attribute__((noreturn));
75 void start_cpu0_default(void) IRAM_ATTR __attribute__((noreturn));
76 #if !CONFIG_FREERTOS_UNICORE
77 static void IRAM_ATTR call_start_cpu1() __attribute__((noreturn));
78 void start_cpu1(void) __attribute__((weak, alias("start_cpu1_default"))) __attribute__((noreturn));
79 void start_cpu1_default(void) IRAM_ATTR __attribute__((noreturn));
80 static bool app_cpu_started = false;
81 #endif //!CONFIG_FREERTOS_UNICORE
83 static void do_global_ctors(void);
84 static void main_task(void* args);
85 extern void app_main(void);
86 extern esp_err_t esp_pthread_init(void);
88 extern int _bss_start;
90 extern int _rtc_bss_start;
91 extern int _rtc_bss_end;
92 extern int _init_start;
93 extern void (*__init_array_start)(void);
94 extern void (*__init_array_end)(void);
95 extern volatile int port_xSchedulerRunning[2];
97 static const char* TAG = "cpu_start";
99 struct object { long placeholder[ 10 ]; };
100 void __register_frame_info (const void *begin, struct object *ob);
101 extern char __eh_frame[];
104 * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
105 * and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
108 void IRAM_ATTR call_start_cpu0()
110 #if CONFIG_FREERTOS_UNICORE
111 RESET_REASON rst_reas[1];
113 RESET_REASON rst_reas[2];
115 cpu_configure_region_protection();
117 //Move exception vectors to IRAM
119 "wsr %0, vecbase\n" \
120 ::"r"(&_init_start));
122 rst_reas[0] = rtc_get_reset_reason(0);
124 #if !CONFIG_FREERTOS_UNICORE
125 rst_reas[1] = rtc_get_reset_reason(1);
128 // from panic handler we can be reset by RWDT or TG0WDT
129 if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET
130 #if !CONFIG_FREERTOS_UNICORE
131 || rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
134 esp_panic_wdt_stop();
137 // Temporary workaround for an ugly crash, until we allow > 192KB of static DRAM
138 if ((intptr_t)&_bss_end > 0x3FFE0000) {
139 // Can't use assert() or logging here because there's no .bss
140 ets_printf("ERROR: Static .bss section extends past 0x3FFE0000. IDF cannot boot.\n");
144 //Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
145 memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
147 /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
148 if (rst_reas[0] != DEEPSLEEP_RESET) {
149 memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
152 #if CONFIG_SPIRAM_BOOT_INIT
153 if (esp_spiram_init() != ESP_OK) {
154 ESP_EARLY_LOGE(TAG, "Failed to init external RAM!");
159 ESP_EARLY_LOGI(TAG, "Pro cpu up.");
161 #if !CONFIG_FREERTOS_UNICORE
162 ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
163 //Flush and enable icache for APP CPU
165 Cache_Read_Enable(1);
167 // Enable clock and reset APP CPU. Note that OpenOCD may have already
168 // enabled clock and taken APP CPU out of reset. In this case don't reset
169 // APP CPU again, as that will clear the breakpoints which may have already
171 if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) {
172 DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
173 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
174 DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
175 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
177 ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
179 while (!app_cpu_started) {
183 ESP_EARLY_LOGI(TAG, "Single core mode");
184 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
188 #if CONFIG_SPIRAM_MEMTEST
189 bool ext_ram_ok=esp_spiram_test();
191 ESP_EARLY_LOGE(TAG, "External RAM failed memory test!");
196 /* Initialize heap allocator. WARNING: This *needs* to happen *after* the app cpu has booted.
197 If the heap allocator is initialized first, it will put free memory linked list items into
198 memory also used by the ROM. Starting the app cpu will let its ROM initialize that memory,
199 corrupting those linked lists. Initializing the allocator *after* the app cpu has booted
200 works around this problem.
201 With SPI RAM enabled, there's a second reason: half of the SPI RAM will be managed by the
202 app CPU, and when that is not up yet, the memory will be inaccessible and heap_caps_init may
203 fail initializing it properly. */
206 ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
210 #if !CONFIG_FREERTOS_UNICORE
212 static void wdt_reset_cpu1_info_enable(void)
214 DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
215 DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
218 void IRAM_ATTR call_start_cpu1()
221 "wsr %0, vecbase\n" \
222 ::"r"(&_init_start));
224 ets_set_appcpu_boot_addr(0);
225 cpu_configure_region_protection();
227 #if CONFIG_CONSOLE_UART_NONE
228 ets_install_putc1(NULL);
229 ets_install_putc2(NULL);
230 #else // CONFIG_CONSOLE_UART_NONE
232 ets_install_uart_printf();
233 uart_tx_switch(CONFIG_CONSOLE_UART_NUM);
236 wdt_reset_cpu1_info_enable();
237 ESP_EARLY_LOGI(TAG, "App cpu up.");
241 #endif //!CONFIG_FREERTOS_UNICORE
243 static void intr_matrix_clear(void)
245 //Clear all the interrupt matrix register
246 for (int i = ETS_WIFI_MAC_INTR_SOURCE; i <= ETS_CACHE_IA_INTR_SOURCE; i++) {
247 intr_matrix_set(0, i, ETS_INVALID_INUM);
248 #if !CONFIG_FREERTOS_UNICORE
249 intr_matrix_set(1, i, ETS_INVALID_INUM);
254 void start_cpu0_default(void)
257 esp_setup_syscall_table();
259 #if CONFIG_SPIRAM_BOOT_INIT && (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC)
260 esp_err_t r=esp_spiram_add_to_heapalloc();
262 ESP_EARLY_LOGE(TAG, "External RAM could not be added to heap!");
265 #if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
266 r=esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL);
268 ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool!");
272 #if CONFIG_SPIRAM_USE_MALLOC
273 heap_caps_malloc_extmem_enable(CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL);
277 //Enable trace memory and immediately start trace.
278 #if CONFIG_ESP32_TRAX
279 #if CONFIG_ESP32_TRAX_TWOBANKS
280 trax_enable(TRAX_ENA_PRO_APP);
282 trax_enable(TRAX_ENA_PRO);
284 trax_start_trace(TRAX_DOWNCOUNT_WORDS);
287 esp_perip_clk_init();
289 #ifndef CONFIG_CONSOLE_UART_NONE
290 uart_div_modify(CONFIG_CONSOLE_UART_NUM, (rtc_clk_apb_freq_get() << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
292 #if CONFIG_BROWNOUT_DET
295 #if CONFIG_DISABLE_BASIC_ROM_CONSOLE
296 esp_efuse_disable_basic_rom_console();
298 rtc_gpio_force_hold_dis_all();
299 esp_vfs_dev_uart_register();
300 esp_reent_init(_GLOBAL_REENT);
301 #ifndef CONFIG_CONSOLE_UART_NONE
302 const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_CONSOLE_UART_NUM);
303 _GLOBAL_REENT->_stdin = fopen(default_uart_dev, "r");
304 _GLOBAL_REENT->_stdout = fopen(default_uart_dev, "w");
305 _GLOBAL_REENT->_stderr = fopen(default_uart_dev, "w");
307 _GLOBAL_REENT->_stdin = (FILE*) &__sf_fake_stdin;
308 _GLOBAL_REENT->_stdout = (FILE*) &__sf_fake_stdout;
309 _GLOBAL_REENT->_stderr = (FILE*) &__sf_fake_stderr;
312 esp_set_time_from_rtc();
313 #if CONFIG_ESP32_APPTRACE_ENABLE
314 err = esp_apptrace_init();
315 assert(err == ESP_OK && "Failed to init apptrace module on PRO CPU!");
317 #if CONFIG_SYSVIEW_ENABLE
318 SEGGER_SYSVIEW_Conf();
320 err = esp_pthread_init();
321 assert(err == ESP_OK && "Failed to init pthread module!");
330 esp_cache_err_int_init();
331 esp_crosscore_int_init();
333 #ifndef CONFIG_FREERTOS_UNICORE
334 esp_dport_access_int_init();
337 /* init default OS-aware flash access critical section */
338 spi_flash_guard_set(&g_flash_guard_default_ops);
340 #if CONFIG_ESP32_ENABLE_COREDUMP
341 esp_core_dump_init();
344 portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
345 ESP_TASK_MAIN_STACK, NULL,
346 ESP_TASK_MAIN_PRIO, NULL, 0);
347 assert(res == pdTRUE);
348 ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
349 vTaskStartScheduler();
350 abort(); /* Only get to here if not enough free heap to start scheduler */
353 #if !CONFIG_FREERTOS_UNICORE
354 void start_cpu1_default(void)
356 // Wait for FreeRTOS initialization to finish on PRO CPU
357 while (port_xSchedulerRunning[0] == 0) {
360 #if CONFIG_ESP32_TRAX_TWOBANKS
361 trax_start_trace(TRAX_DOWNCOUNT_WORDS);
363 #if CONFIG_ESP32_APPTRACE_ENABLE
364 esp_err_t err = esp_apptrace_init();
365 assert(err == ESP_OK && "Failed to init apptrace module on APP CPU!");
367 //Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
368 //has started, but it isn't active *on this CPU* yet.
369 esp_cache_err_int_init();
370 esp_crosscore_int_init();
371 esp_dport_access_int_init();
373 ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
374 xPortStartScheduler();
375 abort(); /* Only get to here if FreeRTOS somehow very broken */
377 #endif //!CONFIG_FREERTOS_UNICORE
379 static void do_global_ctors(void)
381 static struct object ob;
382 __register_frame_info( __eh_frame, &ob );
385 for (p = &__init_array_end - 1; p >= &__init_array_start; --p) {
390 static void main_task(void* args)
392 // Now that the application is about to start, disable boot watchdogs
393 REG_CLR_BIT(TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN_S);
394 REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
395 #if !CONFIG_FREERTOS_UNICORE
396 // Wait for FreeRTOS initialization to finish on APP CPU, before replacing its startup stack
397 while (port_xSchedulerRunning[1] == 0) {
401 //Enable allocation in region where the startup stacks were located.
402 heap_caps_enable_nonos_stack_heaps();