1 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
21 #include "rom/ets_sys.h"
24 #include "rom/cache.h"
28 #include "soc/dport_reg.h"
29 #include "soc/io_mux_reg.h"
30 #include "soc/rtc_cntl_reg.h"
31 #include "soc/timer_group_reg.h"
33 #include "driver/rtc_io.h"
35 #include "freertos/FreeRTOS.h"
36 #include "freertos/task.h"
37 #include "freertos/semphr.h"
38 #include "freertos/queue.h"
39 #include "freertos/portmacro.h"
41 #include "tcpip_adapter.h"
43 #include "esp_heap_caps_init.h"
44 #include "sdkconfig.h"
45 #include "esp_system.h"
46 #include "esp_spi_flash.h"
47 #include "nvs_flash.h"
48 #include "esp_event.h"
49 #include "esp_spi_flash.h"
51 #include "esp_crosscore_int.h"
52 #include "esp_dport_access.h"
54 #include "esp_vfs_dev.h"
55 #include "esp_newlib.h"
56 #include "esp_brownout.h"
57 #include "esp_int_wdt.h"
58 #include "esp_task_wdt.h"
59 #include "esp_phy_init.h"
60 #include "esp_cache_err_int.h"
61 #include "esp_coexist.h"
62 #include "esp_panic.h"
63 #include "esp_core_dump.h"
64 #include "esp_app_trace.h"
65 #include "esp_efuse.h"
66 #include "esp_spiram.h"
67 #include "esp_clk_internal.h"
68 #include "esp_timer.h"
71 #define STRINGIFY(s) STRINGIFY2(s)
72 #define STRINGIFY2(s) #s
74 void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default"))) __attribute__((noreturn));
75 void start_cpu0_default(void) IRAM_ATTR __attribute__((noreturn));
76 #if !CONFIG_FREERTOS_UNICORE
77 static void IRAM_ATTR call_start_cpu1() __attribute__((noreturn));
78 void start_cpu1(void) __attribute__((weak, alias("start_cpu1_default"))) __attribute__((noreturn));
79 void start_cpu1_default(void) IRAM_ATTR __attribute__((noreturn));
80 static bool app_cpu_started = false;
81 #endif //!CONFIG_FREERTOS_UNICORE
83 static void do_global_ctors(void);
84 static void main_task(void* args);
85 extern void app_main(void);
86 extern esp_err_t esp_pthread_init(void);
88 extern int _bss_start;
90 extern int _rtc_bss_start;
91 extern int _rtc_bss_end;
92 extern int _init_start;
93 extern void (*__init_array_start)(void);
94 extern void (*__init_array_end)(void);
95 extern volatile int port_xSchedulerRunning[2];
97 static const char* TAG = "cpu_start";
99 struct object { long placeholder[ 10 ]; };
100 void __register_frame_info (const void *begin, struct object *ob);
101 extern char __eh_frame[];
104 * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
105 * and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
108 void IRAM_ATTR call_start_cpu0()
110 #if CONFIG_FREERTOS_UNICORE
111 RESET_REASON rst_reas[1];
113 RESET_REASON rst_reas[2];
115 cpu_configure_region_protection();
117 //Move exception vectors to IRAM
119 "wsr %0, vecbase\n" \
120 ::"r"(&_init_start));
122 rst_reas[0] = rtc_get_reset_reason(0);
124 #if !CONFIG_FREERTOS_UNICORE
125 rst_reas[1] = rtc_get_reset_reason(1);
128 // from panic handler we can be reset by RWDT or TG0WDT
129 if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET
130 #if !CONFIG_FREERTOS_UNICORE
131 || rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
134 esp_panic_wdt_stop();
137 // Temporary workaround for an ugly crash, until we allow > 192KB of static DRAM
138 if ((intptr_t)&_bss_end > 0x3FFE0000) {
139 // Can't use assert() or logging here because there's no .bss
140 ets_printf("ERROR: Static .bss section extends past 0x3FFE0000. IDF cannot boot.\n");
144 //Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
145 memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
147 /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
148 if (rst_reas[0] != DEEPSLEEP_RESET) {
149 memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
152 #if CONFIG_SPIRAM_BOOT_INIT
153 esp_spiram_init_cache();
154 if (esp_spiram_init() != ESP_OK) {
155 ESP_EARLY_LOGE(TAG, "Failed to init external RAM!");
160 ESP_EARLY_LOGI(TAG, "Pro cpu up.");
162 #if !CONFIG_FREERTOS_UNICORE
163 ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
164 //Flush and enable icache for APP CPU
166 Cache_Read_Enable(1);
168 // Enable clock and reset APP CPU. Note that OpenOCD may have already
169 // enabled clock and taken APP CPU out of reset. In this case don't reset
170 // APP CPU again, as that will clear the breakpoints which may have already
172 if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) {
173 DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
174 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
175 DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
176 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
178 ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
180 while (!app_cpu_started) {
184 ESP_EARLY_LOGI(TAG, "Single core mode");
185 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
189 #if CONFIG_SPIRAM_MEMTEST
190 bool ext_ram_ok=esp_spiram_test();
192 ESP_EARLY_LOGE(TAG, "External RAM failed memory test!");
197 /* Initialize heap allocator. WARNING: This *needs* to happen *after* the app cpu has booted.
198 If the heap allocator is initialized first, it will put free memory linked list items into
199 memory also used by the ROM. Starting the app cpu will let its ROM initialize that memory,
200 corrupting those linked lists. Initializing the allocator *after* the app cpu has booted
201 works around this problem.
202 With SPI RAM enabled, there's a second reason: half of the SPI RAM will be managed by the
203 app CPU, and when that is not up yet, the memory will be inaccessible and heap_caps_init may
204 fail initializing it properly. */
207 ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
211 #if !CONFIG_FREERTOS_UNICORE
213 static void wdt_reset_cpu1_info_enable(void)
215 DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
216 DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
219 void IRAM_ATTR call_start_cpu1()
222 "wsr %0, vecbase\n" \
223 ::"r"(&_init_start));
225 ets_set_appcpu_boot_addr(0);
226 cpu_configure_region_protection();
228 #if CONFIG_CONSOLE_UART_NONE
229 ets_install_putc1(NULL);
230 ets_install_putc2(NULL);
231 #else // CONFIG_CONSOLE_UART_NONE
233 ets_install_uart_printf();
234 uart_tx_switch(CONFIG_CONSOLE_UART_NUM);
237 wdt_reset_cpu1_info_enable();
238 ESP_EARLY_LOGI(TAG, "App cpu up.");
242 #endif //!CONFIG_FREERTOS_UNICORE
244 static void intr_matrix_clear(void)
246 //Clear all the interrupt matrix register
247 for (int i = ETS_WIFI_MAC_INTR_SOURCE; i <= ETS_CACHE_IA_INTR_SOURCE; i++) {
248 intr_matrix_set(0, i, ETS_INVALID_INUM);
249 #if !CONFIG_FREERTOS_UNICORE
250 intr_matrix_set(1, i, ETS_INVALID_INUM);
255 void start_cpu0_default(void)
258 esp_setup_syscall_table();
260 #if CONFIG_SPIRAM_BOOT_INIT && (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC)
261 esp_err_t r=esp_spiram_add_to_heapalloc();
263 ESP_EARLY_LOGE(TAG, "External RAM could not be added to heap!");
266 #if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
267 r=esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL);
269 ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool!");
273 #if CONFIG_SPIRAM_USE_MALLOC
274 heap_caps_malloc_extmem_enable(CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL);
278 //Enable trace memory and immediately start trace.
279 #if CONFIG_ESP32_TRAX
280 #if CONFIG_ESP32_TRAX_TWOBANKS
281 trax_enable(TRAX_ENA_PRO_APP);
283 trax_enable(TRAX_ENA_PRO);
285 trax_start_trace(TRAX_DOWNCOUNT_WORDS);
288 esp_perip_clk_init();
290 #ifndef CONFIG_CONSOLE_UART_NONE
291 uart_div_modify(CONFIG_CONSOLE_UART_NUM, (rtc_clk_apb_freq_get() << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
293 #if CONFIG_BROWNOUT_DET
296 #if CONFIG_DISABLE_BASIC_ROM_CONSOLE
297 esp_efuse_disable_basic_rom_console();
299 rtc_gpio_force_hold_dis_all();
300 esp_vfs_dev_uart_register();
301 esp_reent_init(_GLOBAL_REENT);
302 #ifndef CONFIG_CONSOLE_UART_NONE
303 const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_CONSOLE_UART_NUM);
304 _GLOBAL_REENT->_stdin = fopen(default_uart_dev, "r");
305 _GLOBAL_REENT->_stdout = fopen(default_uart_dev, "w");
306 _GLOBAL_REENT->_stderr = fopen(default_uart_dev, "w");
308 _GLOBAL_REENT->_stdin = (FILE*) &__sf_fake_stdin;
309 _GLOBAL_REENT->_stdout = (FILE*) &__sf_fake_stdout;
310 _GLOBAL_REENT->_stderr = (FILE*) &__sf_fake_stderr;
313 esp_set_time_from_rtc();
314 #if CONFIG_ESP32_APPTRACE_ENABLE
315 err = esp_apptrace_init();
316 assert(err == ESP_OK && "Failed to init apptrace module on PRO CPU!");
318 #if CONFIG_SYSVIEW_ENABLE
319 SEGGER_SYSVIEW_Conf();
321 err = esp_pthread_init();
322 assert(err == ESP_OK && "Failed to init pthread module!");
331 esp_cache_err_int_init();
332 esp_crosscore_int_init();
334 #ifndef CONFIG_FREERTOS_UNICORE
335 esp_dport_access_int_init();
338 /* init default OS-aware flash access critical section */
339 spi_flash_guard_set(&g_flash_guard_default_ops);
341 #if CONFIG_ESP32_ENABLE_COREDUMP
342 esp_core_dump_init();
345 portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
346 ESP_TASK_MAIN_STACK, NULL,
347 ESP_TASK_MAIN_PRIO, NULL, 0);
348 assert(res == pdTRUE);
349 ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
350 vTaskStartScheduler();
351 abort(); /* Only get to here if not enough free heap to start scheduler */
354 #if !CONFIG_FREERTOS_UNICORE
355 void start_cpu1_default(void)
357 // Wait for FreeRTOS initialization to finish on PRO CPU
358 while (port_xSchedulerRunning[0] == 0) {
361 #if CONFIG_ESP32_TRAX_TWOBANKS
362 trax_start_trace(TRAX_DOWNCOUNT_WORDS);
364 #if CONFIG_ESP32_APPTRACE_ENABLE
365 esp_err_t err = esp_apptrace_init();
366 assert(err == ESP_OK && "Failed to init apptrace module on APP CPU!");
368 //Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
369 //has started, but it isn't active *on this CPU* yet.
370 esp_cache_err_int_init();
371 esp_crosscore_int_init();
372 esp_dport_access_int_init();
374 ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
375 xPortStartScheduler();
376 abort(); /* Only get to here if FreeRTOS somehow very broken */
378 #endif //!CONFIG_FREERTOS_UNICORE
380 static void do_global_ctors(void)
382 static struct object ob;
383 __register_frame_info( __eh_frame, &ob );
386 for (p = &__init_array_end - 1; p >= &__init_array_start; --p) {
391 static void main_task(void* args)
393 // Now that the application is about to start, disable boot watchdogs
394 REG_CLR_BIT(TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN_S);
395 REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
396 #if !CONFIG_FREERTOS_UNICORE
397 // Wait for FreeRTOS initialization to finish on APP CPU, before replacing its startup stack
398 while (port_xSchedulerRunning[1] == 0) {
402 //Enable allocation in region where the startup stacks were located.
403 heap_caps_enable_nonos_stack_heaps();