1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
20 #include "rom/ets_sys.h"
23 #include "rom/cache.h"
26 #include "soc/dport_reg.h"
27 #include "soc/io_mux_reg.h"
28 #include "soc/rtc_cntl_reg.h"
29 #include "soc/timer_group_reg.h"
31 #include "driver/rtc_io.h"
33 #include "freertos/FreeRTOS.h"
34 #include "freertos/task.h"
35 #include "freertos/semphr.h"
36 #include "freertos/queue.h"
37 #include "freertos/portmacro.h"
39 #include "tcpip_adapter.h"
41 #include "heap_alloc_caps.h"
42 #include "sdkconfig.h"
43 #include "esp_system.h"
44 #include "esp_spi_flash.h"
45 #include "nvs_flash.h"
46 #include "esp_event.h"
47 #include "esp_spi_flash.h"
49 #include "esp_crosscore_int.h"
51 #include "esp_vfs_dev.h"
52 #include "esp_newlib.h"
53 #include "esp_brownout.h"
54 #include "esp_int_wdt.h"
55 #include "esp_task_wdt.h"
56 #include "esp_phy_init.h"
57 #include "esp_coexist.h"
60 #define STRINGIFY(s) STRINGIFY2(s)
61 #define STRINGIFY2(s) #s
63 void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default")));
64 void start_cpu0_default(void) IRAM_ATTR;
65 #if !CONFIG_FREERTOS_UNICORE
66 static void IRAM_ATTR call_start_cpu1();
67 void start_cpu1(void) __attribute__((weak, alias("start_cpu1_default")));
68 void start_cpu1_default(void) IRAM_ATTR;
69 static bool app_cpu_started = false;
70 #endif //!CONFIG_FREERTOS_UNICORE
72 static void do_global_ctors(void);
73 static void do_phy_init();
74 static void main_task(void* args);
75 extern void app_main(void);
77 extern int _bss_start;
79 extern int _rtc_bss_start;
80 extern int _rtc_bss_end;
81 extern int _init_start;
82 extern void (*__init_array_start)(void);
83 extern void (*__init_array_end)(void);
84 extern volatile int port_xSchedulerRunning[2];
86 static const char* TAG = "cpu_start";
89 * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
90 * and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
93 void IRAM_ATTR call_start_cpu0()
95 cpu_configure_region_protection();
97 //Move exception vectors to IRAM
100 ::"r"(&_init_start));
102 memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
104 /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
105 if (rtc_get_reset_reason(0) != DEEPSLEEP_RESET) {
106 memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
109 // Initialize heap allocator
110 heap_alloc_caps_init();
112 ESP_EARLY_LOGI(TAG, "Pro cpu up.");
114 #if !CONFIG_FREERTOS_UNICORE
115 ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
116 //Flush and enable icache for APP CPU
118 Cache_Read_Enable(1);
120 //Enable clock gating and reset the app cpu.
121 SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
122 CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
123 SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
124 CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
125 ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
127 while (!app_cpu_started) {
131 ESP_EARLY_LOGI(TAG, "Single core mode");
132 CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
134 ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
138 #if !CONFIG_FREERTOS_UNICORE
139 void IRAM_ATTR call_start_cpu1()
142 "wsr %0, vecbase\n" \
143 ::"r"(&_init_start));
145 cpu_configure_region_protection();
147 #if CONFIG_CONSOLE_UART_NONE
148 ets_install_putc1(NULL);
149 ets_install_putc2(NULL);
150 #else // CONFIG_CONSOLE_UART_NONE
152 ets_install_uart_printf();
153 uart_tx_switch(CONFIG_CONSOLE_UART_NUM);
156 ESP_EARLY_LOGI(TAG, "App cpu up.");
160 #endif //!CONFIG_FREERTOS_UNICORE
162 void start_cpu0_default(void)
164 esp_setup_syscall_table();
165 //Enable trace memory and immediately start trace.
166 #if CONFIG_MEMMAP_TRACEMEM
167 #if CONFIG_MEMMAP_TRACEMEM_TWOBANKS
168 trax_enable(TRAX_ENA_PRO_APP);
170 trax_enable(TRAX_ENA_PRO);
172 trax_start_trace(TRAX_DOWNCOUNT_WORDS);
174 esp_set_cpu_freq(); // set CPU frequency configured in menuconfig
175 uart_div_modify(CONFIG_CONSOLE_UART_NUM, (APB_CLK_FREQ << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
176 #if CONFIG_BROWNOUT_DET
179 rtc_gpio_unhold_all();
180 esp_setup_time_syscalls();
181 esp_vfs_dev_uart_register();
182 esp_reent_init(_GLOBAL_REENT);
183 #ifndef CONFIG_CONSOLE_UART_NONE
184 const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_CONSOLE_UART_NUM);
185 _GLOBAL_REENT->_stdin = fopen(default_uart_dev, "r");
186 _GLOBAL_REENT->_stdout = fopen(default_uart_dev, "w");
187 _GLOBAL_REENT->_stderr = fopen(default_uart_dev, "w");
189 _GLOBAL_REENT->_stdin = (FILE*) &__sf_fake_stdin;
190 _GLOBAL_REENT->_stdout = (FILE*) &__sf_fake_stdout;
191 _GLOBAL_REENT->_stderr = (FILE*) &__sf_fake_stderr;
200 #if !CONFIG_FREERTOS_UNICORE
201 esp_crosscore_int_init();
206 #if CONFIG_ESP32_PHY_AUTO_INIT
211 #if CONFIG_SW_COEXIST_ENABLE
212 if (coex_init() == ESP_OK) {
213 coexist_set_enable(true);
217 xTaskCreatePinnedToCore(&main_task, "main",
218 ESP_TASK_MAIN_STACK, NULL,
219 ESP_TASK_MAIN_PRIO, NULL, 0);
220 ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
221 vTaskStartScheduler();
224 #if !CONFIG_FREERTOS_UNICORE
225 void start_cpu1_default(void)
227 #if CONFIG_MEMMAP_TRACEMEM_TWOBANKS
228 trax_start_trace(TRAX_DOWNCOUNT_WORDS);
230 // Wait for FreeRTOS initialization to finish on PRO CPU
231 while (port_xSchedulerRunning[0] == 0) {
234 //Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
235 //has started, but it isn't active *on this CPU* yet.
236 esp_crosscore_int_init();
238 ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
239 xPortStartScheduler();
241 #endif //!CONFIG_FREERTOS_UNICORE
243 static void do_global_ctors(void)
246 for (p = &__init_array_end - 1; p >= &__init_array_start; --p) {
251 static void main_task(void* args)
253 // Now that the application is about to start, disable boot watchdogs
254 REG_CLR_BIT(TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN_S);
255 REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
260 static void do_phy_init()
262 esp_phy_calibration_mode_t calibration_mode = PHY_RF_CAL_PARTIAL;
263 if (rtc_get_reset_reason(0) == DEEPSLEEP_RESET) {
264 calibration_mode = PHY_RF_CAL_NONE;
266 const esp_phy_init_data_t* init_data = esp_phy_get_init_data();
267 if (init_data == NULL) {
268 ESP_LOGE(TAG, "failed to obtain PHY init data");
271 esp_phy_calibration_data_t* cal_data =
272 (esp_phy_calibration_data_t*) calloc(sizeof(esp_phy_calibration_data_t), 1);
273 if (cal_data == NULL) {
274 ESP_LOGE(TAG, "failed to allocate memory for RF calibration data");
277 esp_err_t err = esp_phy_load_cal_data_from_nvs(cal_data);
279 ESP_LOGW(TAG, "failed to load RF calibration data, falling back to full calibration");
280 calibration_mode = PHY_RF_CAL_FULL;
283 esp_phy_init(init_data, calibration_mode, cal_data);
285 if (calibration_mode != PHY_RF_CAL_NONE) {
286 err = esp_phy_store_cal_data_to_nvs(cal_data);
290 esp_phy_release_init_data(init_data);
291 free(cal_data); // PHY maintains a copy of calibration data, so we can free this