1 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
21 #include "rom/ets_sys.h"
24 #include "rom/cache.h"
28 #include "soc/dport_reg.h"
29 #include "soc/io_mux_reg.h"
30 #include "soc/rtc_cntl_reg.h"
31 #include "soc/timer_group_reg.h"
33 #include "driver/rtc_io.h"
35 #include "freertos/FreeRTOS.h"
36 #include "freertos/task.h"
37 #include "freertos/semphr.h"
38 #include "freertos/queue.h"
39 #include "freertos/portmacro.h"
41 #include "tcpip_adapter.h"
43 #include "esp_heap_caps_init.h"
44 #include "sdkconfig.h"
45 #include "esp_system.h"
46 #include "esp_spi_flash.h"
47 #include "nvs_flash.h"
48 #include "esp_event.h"
49 #include "esp_spi_flash.h"
51 #include "esp_crosscore_int.h"
52 #include "esp_dport_access.h"
54 #include "esp_vfs_dev.h"
55 #include "esp_newlib.h"
56 #include "esp_brownout.h"
57 #include "esp_int_wdt.h"
58 #include "esp_task_wdt.h"
59 #include "esp_phy_init.h"
60 #include "esp_cache_err_int.h"
61 #include "esp_coexist.h"
62 #include "esp_panic.h"
63 #include "esp_core_dump.h"
64 #include "esp_app_trace.h"
65 #include "esp_efuse.h"
66 #include "esp_spiram.h"
67 #include "esp_clk_internal.h"
68 #include "esp_timer.h"
73 #define STRINGIFY(s) STRINGIFY2(s)
74 #define STRINGIFY2(s) #s
76 void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default"))) __attribute__((noreturn));
77 void start_cpu0_default(void) IRAM_ATTR __attribute__((noreturn));
78 #if !CONFIG_FREERTOS_UNICORE
79 static void IRAM_ATTR call_start_cpu1() __attribute__((noreturn));
80 void start_cpu1(void) __attribute__((weak, alias("start_cpu1_default"))) __attribute__((noreturn));
81 void start_cpu1_default(void) IRAM_ATTR __attribute__((noreturn));
82 static bool app_cpu_started = false;
83 #endif //!CONFIG_FREERTOS_UNICORE
85 static void do_global_ctors(void);
86 static void main_task(void* args);
87 extern void app_main(void);
88 extern esp_err_t esp_pthread_init(void);
90 extern int _bss_start;
92 extern int _rtc_bss_start;
93 extern int _rtc_bss_end;
94 extern int _init_start;
95 extern void (*__init_array_start)(void);
96 extern void (*__init_array_end)(void);
97 extern volatile int port_xSchedulerRunning[2];
99 static const char* TAG = "cpu_start";
101 struct object { long placeholder[ 10 ]; };
102 void __register_frame_info (const void *begin, struct object *ob);
103 extern char __eh_frame[];
106 * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
107 * and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
110 void IRAM_ATTR call_start_cpu0()
112 #if CONFIG_FREERTOS_UNICORE
113 RESET_REASON rst_reas[1];
115 RESET_REASON rst_reas[2];
117 cpu_configure_region_protection();
119 //Move exception vectors to IRAM
121 "wsr %0, vecbase\n" \
122 ::"r"(&_init_start));
124 rst_reas[0] = rtc_get_reset_reason(0);
126 #if !CONFIG_FREERTOS_UNICORE
127 rst_reas[1] = rtc_get_reset_reason(1);
130 // from panic handler we can be reset by RWDT or TG0WDT
131 if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET
132 #if !CONFIG_FREERTOS_UNICORE
133 || rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
136 esp_panic_wdt_stop();
139 // Temporary workaround for an ugly crash, until we allow > 192KB of static DRAM
140 if ((intptr_t)&_bss_end > 0x3FFE0000) {
141 // Can't use assert() or logging here because there's no .bss
142 ets_printf("ERROR: Static .bss section extends past 0x3FFE0000. IDF cannot boot.\n");
146 //Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
147 memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
149 /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
150 if (rst_reas[0] != DEEPSLEEP_RESET) {
151 memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
154 #if CONFIG_SPIRAM_BOOT_INIT
155 esp_spiram_init_cache();
156 if (esp_spiram_init() != ESP_OK) {
157 ESP_EARLY_LOGE(TAG, "Failed to init external RAM!");
162 ESP_EARLY_LOGI(TAG, "Pro cpu up.");
164 #if !CONFIG_FREERTOS_UNICORE
165 ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
166 //Flush and enable icache for APP CPU
168 Cache_Read_Enable(1);
170 // Enable clock and reset APP CPU. Note that OpenOCD may have already
171 // enabled clock and taken APP CPU out of reset. In this case don't reset
172 // APP CPU again, as that will clear the breakpoints which may have already
174 if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) {
175 DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
176 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
177 DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
178 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
180 ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
182 while (!app_cpu_started) {
186 ESP_EARLY_LOGI(TAG, "Single core mode");
187 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
191 #if CONFIG_SPIRAM_MEMTEST
192 bool ext_ram_ok=esp_spiram_test();
194 ESP_EARLY_LOGE(TAG, "External RAM failed memory test!");
199 /* Initialize heap allocator. WARNING: This *needs* to happen *after* the app cpu has booted.
200 If the heap allocator is initialized first, it will put free memory linked list items into
201 memory also used by the ROM. Starting the app cpu will let its ROM initialize that memory,
202 corrupting those linked lists. Initializing the allocator *after* the app cpu has booted
203 works around this problem.
204 With SPI RAM enabled, there's a second reason: half of the SPI RAM will be managed by the
205 app CPU, and when that is not up yet, the memory will be inaccessible and heap_caps_init may
206 fail initializing it properly. */
209 ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
213 #if !CONFIG_FREERTOS_UNICORE
215 static void wdt_reset_cpu1_info_enable(void)
217 DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
218 DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
221 void IRAM_ATTR call_start_cpu1()
224 "wsr %0, vecbase\n" \
225 ::"r"(&_init_start));
227 ets_set_appcpu_boot_addr(0);
228 cpu_configure_region_protection();
230 #if CONFIG_CONSOLE_UART_NONE
231 ets_install_putc1(NULL);
232 ets_install_putc2(NULL);
233 #else // CONFIG_CONSOLE_UART_NONE
235 ets_install_uart_printf();
236 uart_tx_switch(CONFIG_CONSOLE_UART_NUM);
239 wdt_reset_cpu1_info_enable();
240 ESP_EARLY_LOGI(TAG, "App cpu up.");
244 #endif //!CONFIG_FREERTOS_UNICORE
246 static void intr_matrix_clear(void)
248 //Clear all the interrupt matrix register
249 for (int i = ETS_WIFI_MAC_INTR_SOURCE; i <= ETS_CACHE_IA_INTR_SOURCE; i++) {
250 intr_matrix_set(0, i, ETS_INVALID_INUM);
251 #if !CONFIG_FREERTOS_UNICORE
252 intr_matrix_set(1, i, ETS_INVALID_INUM);
257 void start_cpu0_default(void)
260 esp_setup_syscall_table();
262 #if CONFIG_SPIRAM_BOOT_INIT && (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC)
263 esp_err_t r=esp_spiram_add_to_heapalloc();
265 ESP_EARLY_LOGE(TAG, "External RAM could not be added to heap!");
268 #if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
269 r=esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL);
271 ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool!");
275 #if CONFIG_SPIRAM_USE_MALLOC
276 heap_caps_malloc_extmem_enable(CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL);
280 //Enable trace memory and immediately start trace.
281 #if CONFIG_ESP32_TRAX
282 #if CONFIG_ESP32_TRAX_TWOBANKS
283 trax_enable(TRAX_ENA_PRO_APP);
285 trax_enable(TRAX_ENA_PRO);
287 trax_start_trace(TRAX_DOWNCOUNT_WORDS);
290 esp_perip_clk_init();
293 #ifndef CONFIG_CONSOLE_UART_NONE
294 #ifdef CONFIG_PM_ENABLE
295 const int uart_clk_freq = REF_CLK_FREQ;
296 /* When DFS is enabled, use REFTICK as UART clock source */
297 CLEAR_PERI_REG_MASK(UART_CONF0_REG(CONFIG_CONSOLE_UART_NUM), UART_TICK_REF_ALWAYS_ON);
299 const int uart_clk_freq = APB_CLK_FREQ;
300 #endif // CONFIG_PM_DFS_ENABLE
301 uart_div_modify(CONFIG_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
302 #endif // CONFIG_CONSOLE_UART_NONE
304 #if CONFIG_BROWNOUT_DET
307 #if CONFIG_DISABLE_BASIC_ROM_CONSOLE
308 esp_efuse_disable_basic_rom_console();
310 rtc_gpio_force_hold_dis_all();
311 esp_vfs_dev_uart_register();
312 esp_reent_init(_GLOBAL_REENT);
313 #ifndef CONFIG_CONSOLE_UART_NONE
314 const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_CONSOLE_UART_NUM);
315 _GLOBAL_REENT->_stdin = fopen(default_uart_dev, "r");
316 _GLOBAL_REENT->_stdout = fopen(default_uart_dev, "w");
317 _GLOBAL_REENT->_stderr = fopen(default_uart_dev, "w");
319 _GLOBAL_REENT->_stdin = (FILE*) &__sf_fake_stdin;
320 _GLOBAL_REENT->_stdout = (FILE*) &__sf_fake_stdout;
321 _GLOBAL_REENT->_stderr = (FILE*) &__sf_fake_stderr;
324 esp_set_time_from_rtc();
325 #if CONFIG_ESP32_APPTRACE_ENABLE
326 err = esp_apptrace_init();
327 assert(err == ESP_OK && "Failed to init apptrace module on PRO CPU!");
329 #if CONFIG_SYSVIEW_ENABLE
330 SEGGER_SYSVIEW_Conf();
332 err = esp_pthread_init();
333 assert(err == ESP_OK && "Failed to init pthread module!");
339 esp_cache_err_int_init();
340 esp_crosscore_int_init();
342 #ifndef CONFIG_FREERTOS_UNICORE
343 esp_dport_access_int_init();
346 /* init default OS-aware flash access critical section */
347 spi_flash_guard_set(&g_flash_guard_default_ops);
348 #ifdef CONFIG_PM_ENABLE
350 #ifdef CONFIG_PM_DFS_INIT_AUTO
351 rtc_cpu_freq_t max_freq;
352 rtc_clk_cpu_freq_from_mhz(CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ, &max_freq);
353 esp_pm_config_esp32_t cfg = {
354 .max_cpu_freq = max_freq,
355 .min_cpu_freq = RTC_CPU_FREQ_XTAL
357 esp_pm_configure(&cfg);
358 #endif //CONFIG_PM_DFS_INIT_AUTO
359 #endif //CONFIG_PM_ENABLE
361 #if CONFIG_ESP32_ENABLE_COREDUMP
362 esp_core_dump_init();
365 portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
366 ESP_TASK_MAIN_STACK, NULL,
367 ESP_TASK_MAIN_PRIO, NULL, 0);
368 assert(res == pdTRUE);
369 ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
370 vTaskStartScheduler();
371 abort(); /* Only get to here if not enough free heap to start scheduler */
374 #if !CONFIG_FREERTOS_UNICORE
375 void start_cpu1_default(void)
377 // Wait for FreeRTOS initialization to finish on PRO CPU
378 while (port_xSchedulerRunning[0] == 0) {
381 #if CONFIG_ESP32_TRAX_TWOBANKS
382 trax_start_trace(TRAX_DOWNCOUNT_WORDS);
384 #if CONFIG_ESP32_APPTRACE_ENABLE
385 esp_err_t err = esp_apptrace_init();
386 assert(err == ESP_OK && "Failed to init apptrace module on APP CPU!");
388 //Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
389 //has started, but it isn't active *on this CPU* yet.
390 esp_cache_err_int_init();
391 esp_crosscore_int_init();
392 esp_dport_access_int_init();
394 ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
395 xPortStartScheduler();
396 abort(); /* Only get to here if FreeRTOS somehow very broken */
398 #endif //!CONFIG_FREERTOS_UNICORE
400 static void do_global_ctors(void)
402 #ifdef CONFIG_CXX_EXCEPTIONS
403 static struct object ob;
404 __register_frame_info( __eh_frame, &ob );
408 for (p = &__init_array_end - 1; p >= &__init_array_start; --p) {
413 static void main_task(void* args)
415 // Now that the application is about to start, disable boot watchdogs
416 REG_CLR_BIT(TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN_S);
417 REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
418 #if !CONFIG_FREERTOS_UNICORE
419 // Wait for FreeRTOS initialization to finish on APP CPU, before replacing its startup stack
420 while (port_xSchedulerRunning[1] == 0) {
424 //Enable allocation in region where the startup stacks were located.
425 heap_caps_enable_nonos_stack_heaps();
427 //Initialize task wdt if configured to do so
428 #ifdef CONFIG_TASK_WDT_PANIC
429 ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_TASK_WDT_TIMEOUT_S, true))
430 #elif CONFIG_TASK_WDT
431 ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_TASK_WDT_TIMEOUT_S, false))
434 //Add IDLE 0 to task wdt
435 #ifdef CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0
436 TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
438 ESP_ERROR_CHECK(esp_task_wdt_add(idle_0))
441 //Add IDLE 1 to task wdt
442 #ifdef CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1
443 TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1);
445 ESP_ERROR_CHECK(esp_task_wdt_add(idle_1))