1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
15 #include "esp_types.h"
18 #include "esp_intr_alloc.h"
23 #include "freertos/FreeRTOS.h"
24 #include "freertos/semphr.h"
25 #include "freertos/xtensa_api.h"
26 #include "freertos/task.h"
27 #include "freertos/ringbuf.h"
28 #include "soc/dport_reg.h"
29 #include "soc/uart_struct.h"
30 #include "driver/uart.h"
31 #include "driver/gpio.h"
32 #include "driver/uart_select.h"
34 #define XOFF (char)0x13
35 #define XON (char)0x11
37 static const char* UART_TAG = "uart";
38 #define UART_CHECK(a, str, ret_val) \
40 ESP_LOGE(UART_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
44 #define UART_EMPTY_THRESH_DEFAULT (10)
45 #define UART_FULL_THRESH_DEFAULT (120)
46 #define UART_TOUT_THRESH_DEFAULT (10)
47 #define UART_CLKDIV_FRAG_BIT_WIDTH (3)
48 #define UART_TOUT_REF_FACTOR_DEFAULT (UART_CLK_FREQ/(REF_CLK_FREQ<<UART_CLKDIV_FRAG_BIT_WIDTH))
49 #define UART_TX_IDLE_NUM_DEFAULT (0)
50 #define UART_PATTERN_DET_QLEN_DEFAULT (10)
52 #define UART_ENTER_CRITICAL_ISR(mux) portENTER_CRITICAL_ISR(mux)
53 #define UART_EXIT_CRITICAL_ISR(mux) portEXIT_CRITICAL_ISR(mux)
54 #define UART_ENTER_CRITICAL(mux) portENTER_CRITICAL(mux)
55 #define UART_EXIT_CRITICAL(mux) portEXIT_CRITICAL(mux)
57 // Check actual UART mode set
58 #define UART_IS_MODE_SET(uart_number, mode) ((p_uart_obj[uart_number]->uart_mode == mode))
61 uart_event_type_t type; /*!< UART TX data type */
77 uart_port_t uart_num; /*!< UART port number*/
78 int queue_size; /*!< UART event queue size*/
79 QueueHandle_t xQueueUart; /*!< UART queue handler*/
80 intr_handle_t intr_handle; /*!< UART interrupt handle*/
81 uart_mode_t uart_mode; /*!< UART controller actual mode set by uart_set_mode() */
82 bool coll_det_flg; /*!< UART collision detection flag */
85 int rx_buffered_len; /*!< UART cached data length */
86 SemaphoreHandle_t rx_mux; /*!< UART RX data mutex*/
87 int rx_buf_size; /*!< RX ring buffer size */
88 RingbufHandle_t rx_ring_buf; /*!< RX ring buffer handler*/
89 bool rx_buffer_full_flg; /*!< RX ring buffer full flag. */
90 int rx_cur_remain; /*!< Data number that waiting to be read out in ring buffer item*/
91 uint8_t* rx_ptr; /*!< pointer to the current data in ring buffer*/
92 uint8_t* rx_head_ptr; /*!< pointer to the head of RX item*/
93 uint8_t rx_data_buf[UART_FIFO_LEN]; /*!< Data buffer to stash FIFO data*/
94 uint8_t rx_stash_len; /*!< stashed data length.(When using flow control, after reading out FIFO data, if we fail to push to buffer, we can just stash them.) */
95 uart_pat_rb_t rx_pattern_pos;
98 SemaphoreHandle_t tx_fifo_sem; /*!< UART TX FIFO semaphore*/
99 SemaphoreHandle_t tx_mux; /*!< UART TX mutex*/
100 SemaphoreHandle_t tx_done_sem; /*!< UART TX done semaphore*/
101 SemaphoreHandle_t tx_brk_sem; /*!< UART TX send break done semaphore*/
102 int tx_buf_size; /*!< TX ring buffer size */
103 RingbufHandle_t tx_ring_buf; /*!< TX ring buffer handler*/
104 bool tx_waiting_fifo; /*!< this flag indicates that some task is waiting for FIFO empty interrupt, used to send all data without any data buffer*/
105 uint8_t* tx_ptr; /*!< TX data pointer to push to FIFO in TX buffer mode*/
106 uart_tx_data_t* tx_head; /*!< TX data pointer to head of the current buffer in TX ring buffer*/
107 uint32_t tx_len_tot; /*!< Total length of current item in ring buffer*/
109 uint8_t tx_brk_flg; /*!< Flag to indicate to send a break signal in the end of the item sending procedure */
110 uint8_t tx_brk_len; /*!< TX break signal cycle length/number */
111 uint8_t tx_waiting_brk; /*!< Flag to indicate that TX FIFO is ready to send break signal after FIFO is empty, do not push data into TX FIFO right now.*/
112 uart_select_notif_callback_t uart_select_notif_callback; /*!< Notification about select() events */
115 static uart_obj_t *p_uart_obj[UART_NUM_MAX] = {0};
116 /* DRAM_ATTR is required to avoid UART array placed in flash, due to accessed from ISR */
117 static DRAM_ATTR uart_dev_t* const UART[UART_NUM_MAX] = {&UART0, &UART1, &UART2};
118 static portMUX_TYPE uart_spinlock[UART_NUM_MAX] = {portMUX_INITIALIZER_UNLOCKED, portMUX_INITIALIZER_UNLOCKED, portMUX_INITIALIZER_UNLOCKED};
119 static portMUX_TYPE uart_selectlock = portMUX_INITIALIZER_UNLOCKED;
121 esp_err_t uart_set_word_length(uart_port_t uart_num, uart_word_length_t data_bit)
123 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
124 UART_CHECK((data_bit < UART_DATA_BITS_MAX), "data bit error", ESP_FAIL);
125 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
126 UART[uart_num]->conf0.bit_num = data_bit;
127 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
131 esp_err_t uart_get_word_length(uart_port_t uart_num, uart_word_length_t* data_bit)
133 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
134 *(data_bit) = UART[uart_num]->conf0.bit_num;
138 esp_err_t uart_set_stop_bits(uart_port_t uart_num, uart_stop_bits_t stop_bit)
140 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
141 UART_CHECK((stop_bit < UART_STOP_BITS_MAX), "stop bit error", ESP_FAIL);
143 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
144 //workaround for hardware bug, when uart stop bit set as 2-bit mode.
145 if (stop_bit == UART_STOP_BITS_2) {
146 stop_bit = UART_STOP_BITS_1;
147 UART[uart_num]->rs485_conf.dl1_en = 1;
149 UART[uart_num]->rs485_conf.dl1_en = 0;
151 UART[uart_num]->conf0.stop_bit_num = stop_bit;
152 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
156 esp_err_t uart_get_stop_bits(uart_port_t uart_num, uart_stop_bits_t* stop_bit)
158 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
159 //workaround for hardware bug, when uart stop bit set as 2-bit mode.
160 if (UART[uart_num]->rs485_conf.dl1_en == 1 && UART[uart_num]->conf0.stop_bit_num == UART_STOP_BITS_1) {
161 (*stop_bit) = UART_STOP_BITS_2;
163 (*stop_bit) = UART[uart_num]->conf0.stop_bit_num;
168 esp_err_t uart_set_parity(uart_port_t uart_num, uart_parity_t parity_mode)
170 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
171 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
172 UART[uart_num]->conf0.parity = parity_mode & 0x1;
173 UART[uart_num]->conf0.parity_en = (parity_mode >> 1) & 0x1;
174 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
178 esp_err_t uart_get_parity(uart_port_t uart_num, uart_parity_t* parity_mode)
180 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
181 int val = UART[uart_num]->conf0.val;
182 if(val & UART_PARITY_EN_M) {
183 if(val & UART_PARITY_M) {
184 (*parity_mode) = UART_PARITY_ODD;
186 (*parity_mode) = UART_PARITY_EVEN;
189 (*parity_mode) = UART_PARITY_DISABLE;
194 esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baud_rate)
196 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
197 esp_err_t ret = ESP_OK;
198 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
200 if (UART[uart_num]->conf0.tick_ref_always_on == 0) {
201 /* this UART has been configured to use REF_TICK */
202 uart_clk_freq = REF_CLK_FREQ;
204 uart_clk_freq = esp_clk_apb_freq();
206 uint32_t clk_div = (((uart_clk_freq) << 4) / baud_rate);
208 /* baud rate is too high for this clock frequency */
209 ret = ESP_ERR_INVALID_ARG;
211 UART[uart_num]->clk_div.div_int = clk_div >> 4;
212 UART[uart_num]->clk_div.div_frag = clk_div & 0xf;
214 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
218 esp_err_t uart_get_baudrate(uart_port_t uart_num, uint32_t* baudrate)
220 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
221 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
222 uint32_t clk_div = (UART[uart_num]->clk_div.div_int << 4) | UART[uart_num]->clk_div.div_frag;
223 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
224 uint32_t uart_clk_freq = esp_clk_apb_freq();
225 if(UART[uart_num]->conf0.tick_ref_always_on == 0) {
226 uart_clk_freq = REF_CLK_FREQ;
228 (*baudrate) = ((uart_clk_freq) << 4) / clk_div;
232 esp_err_t uart_set_line_inverse(uart_port_t uart_num, uint32_t inverse_mask)
234 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
235 UART_CHECK((((inverse_mask & ~UART_LINE_INV_MASK) == 0) || (inverse_mask == 0)), "inverse_mask error", ESP_FAIL);
236 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
237 CLEAR_PERI_REG_MASK(UART_CONF0_REG(uart_num), UART_LINE_INV_MASK);
238 SET_PERI_REG_MASK(UART_CONF0_REG(uart_num), inverse_mask);
239 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
243 esp_err_t uart_set_sw_flow_ctrl(uart_port_t uart_num, bool enable, uint8_t rx_thresh_xon, uint8_t rx_thresh_xoff)
245 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
246 UART_CHECK((rx_thresh_xon < UART_FIFO_LEN), "rx flow xon thresh error", ESP_FAIL);
247 UART_CHECK((rx_thresh_xoff < UART_FIFO_LEN), "rx flow xon thresh error", ESP_FAIL);
248 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
249 UART[uart_num]->flow_conf.sw_flow_con_en = enable? 1:0;
250 UART[uart_num]->flow_conf.xonoff_del = enable?1:0;
251 UART[uart_num]->swfc_conf.xon_threshold = rx_thresh_xon;
252 UART[uart_num]->swfc_conf.xoff_threshold = rx_thresh_xoff;
253 UART[uart_num]->swfc_conf.xon_char = XON;
254 UART[uart_num]->swfc_conf.xoff_char = XOFF;
255 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
259 //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
260 esp_err_t uart_set_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t flow_ctrl, uint8_t rx_thresh)
262 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
263 UART_CHECK((rx_thresh < UART_FIFO_LEN), "rx flow thresh error", ESP_FAIL);
264 UART_CHECK((flow_ctrl < UART_HW_FLOWCTRL_MAX), "hw_flowctrl mode error", ESP_FAIL);
265 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
266 if(flow_ctrl & UART_HW_FLOWCTRL_RTS) {
267 UART[uart_num]->conf1.rx_flow_thrhd = rx_thresh;
268 UART[uart_num]->conf1.rx_flow_en = 1;
270 UART[uart_num]->conf1.rx_flow_en = 0;
272 if(flow_ctrl & UART_HW_FLOWCTRL_CTS) {
273 UART[uart_num]->conf0.tx_flow_en = 1;
275 UART[uart_num]->conf0.tx_flow_en = 0;
277 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
281 esp_err_t uart_get_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t* flow_ctrl)
283 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
284 uart_hw_flowcontrol_t val = UART_HW_FLOWCTRL_DISABLE;
285 if(UART[uart_num]->conf1.rx_flow_en) {
286 val |= UART_HW_FLOWCTRL_RTS;
288 if(UART[uart_num]->conf0.tx_flow_en) {
289 val |= UART_HW_FLOWCTRL_CTS;
295 static esp_err_t uart_reset_rx_fifo(uart_port_t uart_num)
297 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
298 //Due to hardware issue, we can not use fifo_rst to reset uart fifo.
299 //See description about UART_TXFIFO_RST and UART_RXFIFO_RST in <<esp32_technical_reference_manual>> v2.6 or later.
301 // we read the data out and make `fifo_len == 0 && rd_addr == wr_addr`.
302 while(UART[uart_num]->status.rxfifo_cnt != 0 || (UART[uart_num]->mem_rx_status.wr_addr != UART[uart_num]->mem_rx_status.rd_addr)) {
303 READ_PERI_REG(UART_FIFO_REG(uart_num));
308 esp_err_t uart_clear_intr_status(uart_port_t uart_num, uint32_t clr_mask)
310 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
311 //intr_clr register is write-only
312 UART[uart_num]->int_clr.val = clr_mask;
316 esp_err_t uart_enable_intr_mask(uart_port_t uart_num, uint32_t enable_mask)
318 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
319 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
320 SET_PERI_REG_MASK(UART_INT_CLR_REG(uart_num), enable_mask);
321 SET_PERI_REG_MASK(UART_INT_ENA_REG(uart_num), enable_mask);
322 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
326 esp_err_t uart_disable_intr_mask(uart_port_t uart_num, uint32_t disable_mask)
328 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
329 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
330 CLEAR_PERI_REG_MASK(UART_INT_ENA_REG(uart_num), disable_mask);
331 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
335 static esp_err_t uart_pattern_link_free(uart_port_t uart_num)
337 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
338 if (p_uart_obj[uart_num]->rx_pattern_pos.data != NULL) {
339 int* pdata = p_uart_obj[uart_num]->rx_pattern_pos.data;
340 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
341 p_uart_obj[uart_num]->rx_pattern_pos.data = NULL;
342 p_uart_obj[uart_num]->rx_pattern_pos.wr = 0;
343 p_uart_obj[uart_num]->rx_pattern_pos.rd = 0;
344 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
350 static esp_err_t uart_pattern_enqueue(uart_port_t uart_num, int pos)
352 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
353 esp_err_t ret = ESP_OK;
354 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
355 uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
356 int next = p_pos->wr + 1;
357 if (next >= p_pos->len) {
360 if (next == p_pos->rd) {
361 ESP_EARLY_LOGW(UART_TAG, "Fail to enqueue pattern position, pattern queue is full.");
364 p_pos->data[p_pos->wr] = pos;
368 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
372 static esp_err_t uart_pattern_dequeue(uart_port_t uart_num)
374 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
375 if(p_uart_obj[uart_num]->rx_pattern_pos.data == NULL) {
376 return ESP_ERR_INVALID_STATE;
378 esp_err_t ret = ESP_OK;
379 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
380 uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
381 if (p_pos->rd == p_pos->wr) {
386 if (p_pos->rd >= p_pos->len) {
389 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
394 static esp_err_t uart_pattern_queue_update(uart_port_t uart_num, int diff_len)
396 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
397 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
398 uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
400 while(rd != p_pos->wr) {
401 p_pos->data[rd] -= diff_len;
404 if (rd >= p_pos->len) {
407 if (p_pos->data[rd_rec] < 0) {
411 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
415 int uart_pattern_pop_pos(uart_port_t uart_num)
417 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
418 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
419 uart_pat_rb_t* pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
421 if (pat_pos != NULL && pat_pos->rd != pat_pos->wr) {
422 pos = pat_pos->data[pat_pos->rd];
423 uart_pattern_dequeue(uart_num);
425 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
429 int uart_pattern_get_pos(uart_port_t uart_num)
431 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
432 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
433 uart_pat_rb_t* pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
435 if (pat_pos != NULL && pat_pos->rd != pat_pos->wr) {
436 pos = pat_pos->data[pat_pos->rd];
438 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
442 esp_err_t uart_pattern_queue_reset(uart_port_t uart_num, int queue_length)
444 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
445 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_ERR_INVALID_STATE);
447 int* pdata = (int*) malloc(queue_length * sizeof(int));
449 return ESP_ERR_NO_MEM;
451 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
452 int* ptmp = p_uart_obj[uart_num]->rx_pattern_pos.data;
453 p_uart_obj[uart_num]->rx_pattern_pos.data = pdata;
454 p_uart_obj[uart_num]->rx_pattern_pos.len = queue_length;
455 p_uart_obj[uart_num]->rx_pattern_pos.rd = 0;
456 p_uart_obj[uart_num]->rx_pattern_pos.wr = 0;
457 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
462 esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle)
464 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
465 UART_CHECK(chr_tout >= 0 && chr_tout <= UART_RX_GAP_TOUT_V, "uart pattern set error\n", ESP_FAIL);
466 UART_CHECK(post_idle >= 0 && post_idle <= UART_POST_IDLE_NUM_V, "uart pattern set error\n", ESP_FAIL);
467 UART_CHECK(pre_idle >= 0 && pre_idle <= UART_PRE_IDLE_NUM_V, "uart pattern set error\n", ESP_FAIL);
468 UART[uart_num]->at_cmd_char.data = pattern_chr;
469 UART[uart_num]->at_cmd_char.char_num = chr_num;
470 UART[uart_num]->at_cmd_gaptout.rx_gap_tout = chr_tout;
471 UART[uart_num]->at_cmd_postcnt.post_idle_num = post_idle;
472 UART[uart_num]->at_cmd_precnt.pre_idle_num = pre_idle;
473 return uart_enable_intr_mask(uart_num, UART_AT_CMD_CHAR_DET_INT_ENA_M);
476 esp_err_t uart_disable_pattern_det_intr(uart_port_t uart_num)
478 return uart_disable_intr_mask(uart_num, UART_AT_CMD_CHAR_DET_INT_ENA_M);
481 esp_err_t uart_enable_rx_intr(uart_port_t uart_num)
483 return uart_enable_intr_mask(uart_num, UART_RXFIFO_FULL_INT_ENA|UART_RXFIFO_TOUT_INT_ENA);
486 esp_err_t uart_disable_rx_intr(uart_port_t uart_num)
488 return uart_disable_intr_mask(uart_num, UART_RXFIFO_FULL_INT_ENA|UART_RXFIFO_TOUT_INT_ENA);
491 esp_err_t uart_disable_tx_intr(uart_port_t uart_num)
493 return uart_disable_intr_mask(uart_num, UART_TXFIFO_EMPTY_INT_ENA);
496 esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh)
498 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
499 UART_CHECK((thresh < UART_FIFO_LEN), "empty intr threshold error", ESP_FAIL);
500 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
501 UART[uart_num]->int_clr.txfifo_empty = 1;
502 UART[uart_num]->conf1.txfifo_empty_thrhd = thresh & UART_TXFIFO_EMPTY_THRHD_V;
503 UART[uart_num]->int_ena.txfifo_empty = enable & 0x1;
504 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
508 esp_err_t uart_isr_register(uart_port_t uart_num, void (*fn)(void*), void * arg, int intr_alloc_flags, uart_isr_handle_t *handle)
511 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
512 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
515 ret=esp_intr_alloc(ETS_UART1_INTR_SOURCE, intr_alloc_flags, fn, arg, handle);
518 ret=esp_intr_alloc(ETS_UART2_INTR_SOURCE, intr_alloc_flags, fn, arg, handle);
522 ret=esp_intr_alloc(ETS_UART0_INTR_SOURCE, intr_alloc_flags, fn, arg, handle);
525 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
530 esp_err_t uart_isr_free(uart_port_t uart_num)
533 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
534 if (p_uart_obj[uart_num]->intr_handle==NULL) return ESP_ERR_INVALID_ARG;
535 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
536 ret=esp_intr_free(p_uart_obj[uart_num]->intr_handle);
537 p_uart_obj[uart_num]->intr_handle=NULL;
538 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
542 //internal signal can be output to multiple GPIO pads
543 //only one GPIO pad can connect with input signal
544 esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int rts_io_num, int cts_io_num)
546 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
547 UART_CHECK((tx_io_num < 0 || (GPIO_IS_VALID_OUTPUT_GPIO(tx_io_num))), "tx_io_num error", ESP_FAIL);
548 UART_CHECK((rx_io_num < 0 || (GPIO_IS_VALID_GPIO(rx_io_num))), "rx_io_num error", ESP_FAIL);
549 UART_CHECK((rts_io_num < 0 || (GPIO_IS_VALID_OUTPUT_GPIO(rts_io_num))), "rts_io_num error", ESP_FAIL);
550 UART_CHECK((cts_io_num < 0 || (GPIO_IS_VALID_GPIO(cts_io_num))), "cts_io_num error", ESP_FAIL);
552 int tx_sig, rx_sig, rts_sig, cts_sig;
555 tx_sig = U0TXD_OUT_IDX;
556 rx_sig = U0RXD_IN_IDX;
557 rts_sig = U0RTS_OUT_IDX;
558 cts_sig = U0CTS_IN_IDX;
561 tx_sig = U1TXD_OUT_IDX;
562 rx_sig = U1RXD_IN_IDX;
563 rts_sig = U1RTS_OUT_IDX;
564 cts_sig = U1CTS_IN_IDX;
567 tx_sig = U2TXD_OUT_IDX;
568 rx_sig = U2RXD_IN_IDX;
569 rts_sig = U2RTS_OUT_IDX;
570 cts_sig = U2CTS_IN_IDX;
574 tx_sig = U0TXD_OUT_IDX;
575 rx_sig = U0RXD_IN_IDX;
576 rts_sig = U0RTS_OUT_IDX;
577 cts_sig = U0CTS_IN_IDX;
581 PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[tx_io_num], PIN_FUNC_GPIO);
582 gpio_set_level(tx_io_num, 1);
583 gpio_matrix_out(tx_io_num, tx_sig, 0, 0);
587 PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[rx_io_num], PIN_FUNC_GPIO);
588 gpio_set_pull_mode(rx_io_num, GPIO_PULLUP_ONLY);
589 gpio_set_direction(rx_io_num, GPIO_MODE_INPUT);
590 gpio_matrix_in(rx_io_num, rx_sig, 0);
592 if(rts_io_num >= 0) {
593 PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[rts_io_num], PIN_FUNC_GPIO);
594 gpio_set_direction(rts_io_num, GPIO_MODE_OUTPUT);
595 gpio_matrix_out(rts_io_num, rts_sig, 0, 0);
597 if(cts_io_num >= 0) {
598 PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[cts_io_num], PIN_FUNC_GPIO);
599 gpio_set_pull_mode(cts_io_num, GPIO_PULLUP_ONLY);
600 gpio_set_direction(cts_io_num, GPIO_MODE_INPUT);
601 gpio_matrix_in(cts_io_num, cts_sig, 0);
606 esp_err_t uart_set_rts(uart_port_t uart_num, int level)
608 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
609 UART_CHECK((UART[uart_num]->conf1.rx_flow_en != 1), "disable hw flowctrl before using sw control", ESP_FAIL);
610 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
611 UART[uart_num]->conf0.sw_rts = level & 0x1;
612 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
616 esp_err_t uart_set_dtr(uart_port_t uart_num, int level)
618 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
619 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
620 UART[uart_num]->conf0.sw_dtr = level & 0x1;
621 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
625 esp_err_t uart_set_tx_idle_num(uart_port_t uart_num, uint16_t idle_num)
627 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
628 UART_CHECK((idle_num <= UART_TX_IDLE_NUM_V), "uart idle num error", ESP_FAIL);
630 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
631 UART[uart_num]->idle_conf.tx_idle_num = idle_num;
632 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
636 esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_config)
639 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
640 UART_CHECK((uart_config), "param null", ESP_FAIL);
641 if(uart_num == UART_NUM_0) {
642 periph_module_enable(PERIPH_UART0_MODULE);
643 } else if(uart_num == UART_NUM_1) {
644 periph_module_enable(PERIPH_UART1_MODULE);
645 } else if(uart_num == UART_NUM_2) {
646 periph_module_enable(PERIPH_UART2_MODULE);
648 r = uart_set_hw_flow_ctrl(uart_num, uart_config->flow_ctrl, uart_config->rx_flow_ctrl_thresh);
649 if (r != ESP_OK) return r;
651 UART[uart_num]->conf0.val =
652 (uart_config->parity << UART_PARITY_S)
653 | (uart_config->data_bits << UART_BIT_NUM_S)
654 | ((uart_config->flow_ctrl & UART_HW_FLOWCTRL_CTS) ? UART_TX_FLOW_EN : 0x0)
655 | (uart_config->use_ref_tick ? 0 : UART_TICK_REF_ALWAYS_ON_M);
657 r = uart_set_baudrate(uart_num, uart_config->baud_rate);
658 if (r != ESP_OK) return r;
659 r = uart_set_tx_idle_num(uart_num, UART_TX_IDLE_NUM_DEFAULT);
660 if (r != ESP_OK) return r;
661 r = uart_set_stop_bits(uart_num, uart_config->stop_bits);
662 //A hardware reset does not reset the fifo,
663 //so we need to reset the fifo manually.
664 uart_reset_rx_fifo(uart_num);
668 esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_conf)
670 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
671 UART_CHECK((intr_conf), "param null", ESP_FAIL);
672 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
673 UART[uart_num]->int_clr.val = UART_INTR_MASK;
674 if(intr_conf->intr_enable_mask & UART_RXFIFO_TOUT_INT_ENA_M) {
675 //Hardware issue workaround: when using ref_tick, the rx timeout threshold needs increase to 10 times.
676 //T_ref = T_apb * APB_CLK/(REF_TICK << CLKDIV_FRAG_BIT_WIDTH)
677 if(UART[uart_num]->conf0.tick_ref_always_on == 0) {
678 UART[uart_num]->conf1.rx_tout_thrhd = ((intr_conf->rx_timeout_thresh * UART_TOUT_REF_FACTOR_DEFAULT) & UART_RX_TOUT_THRHD_V);
680 UART[uart_num]->conf1.rx_tout_thrhd = ((intr_conf->rx_timeout_thresh) & UART_RX_TOUT_THRHD_V);
682 UART[uart_num]->conf1.rx_tout_en = 1;
684 UART[uart_num]->conf1.rx_tout_en = 0;
686 if(intr_conf->intr_enable_mask & UART_RXFIFO_FULL_INT_ENA_M) {
687 UART[uart_num]->conf1.rxfifo_full_thrhd = intr_conf->rxfifo_full_thresh;
689 if(intr_conf->intr_enable_mask & UART_TXFIFO_EMPTY_INT_ENA_M) {
690 UART[uart_num]->conf1.txfifo_empty_thrhd = intr_conf->txfifo_empty_intr_thresh;
692 UART[uart_num]->int_ena.val = intr_conf->intr_enable_mask;
693 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
697 static int uart_find_pattern_from_last(uint8_t* buf, int length, uint8_t pat_chr, int pat_num)
702 if (buf[len] == pat_chr) {
707 if (cnt >= pat_num) {
715 //internal isr handler for default driver code.
716 static void uart_rx_intr_handler_default(void *param)
718 uart_obj_t *p_uart = (uart_obj_t*) param;
719 uint8_t uart_num = p_uart->uart_num;
720 uart_dev_t* uart_reg = UART[uart_num];
721 int rx_fifo_len = uart_reg->status.rxfifo_cnt;
723 uint32_t uart_intr_status = UART[uart_num]->int_st.val;
724 uart_event_t uart_event;
725 portBASE_TYPE HPTaskAwoken = 0;
726 static uint8_t pat_flg = 0;
727 while(uart_intr_status != 0x0) {
729 uart_event.type = UART_EVENT_MAX;
730 if(uart_intr_status & UART_TXFIFO_EMPTY_INT_ST_M) {
731 uart_clear_intr_status(uart_num, UART_TXFIFO_EMPTY_INT_CLR_M);
732 uart_disable_intr_mask(uart_num, UART_TXFIFO_EMPTY_INT_ENA_M);
733 if(p_uart->tx_waiting_brk) {
736 //TX semaphore will only be used when tx_buf_size is zero.
737 if(p_uart->tx_waiting_fifo == true && p_uart->tx_buf_size == 0) {
738 p_uart->tx_waiting_fifo = false;
739 xSemaphoreGiveFromISR(p_uart->tx_fifo_sem, &HPTaskAwoken);
740 if(HPTaskAwoken == pdTRUE) {
741 portYIELD_FROM_ISR();
744 //We don't use TX ring buffer, because the size is zero.
745 if(p_uart->tx_buf_size == 0) {
748 int tx_fifo_rem = UART_FIFO_LEN - UART[uart_num]->status.txfifo_cnt;
749 bool en_tx_flg = false;
750 //We need to put a loop here, in case all the buffer items are very short.
751 //That would cause a watch_dog reset because empty interrupt happens so often.
752 //Although this is a loop in ISR, this loop will execute at most 128 turns.
754 if(p_uart->tx_len_tot == 0 || p_uart->tx_ptr == NULL || p_uart->tx_len_cur == 0) {
756 p_uart->tx_head = (uart_tx_data_t*) xRingbufferReceiveFromISR(p_uart->tx_ring_buf, &size);
757 if(p_uart->tx_head) {
758 //The first item is the data description
759 //Get the first item to get the data information
760 if(p_uart->tx_len_tot == 0) {
761 p_uart->tx_ptr = NULL;
762 p_uart->tx_len_tot = p_uart->tx_head->tx_data.size;
763 if(p_uart->tx_head->type == UART_DATA_BREAK) {
764 p_uart->tx_len_tot = p_uart->tx_head->tx_data.size;
765 p_uart->tx_brk_flg = 1;
766 p_uart->tx_brk_len = p_uart->tx_head->tx_data.brk_len;
768 //We have saved the data description from the 1st item, return buffer.
769 vRingbufferReturnItemFromISR(p_uart->tx_ring_buf, p_uart->tx_head, &HPTaskAwoken);
770 if(HPTaskAwoken == pdTRUE) {
771 portYIELD_FROM_ISR();
773 }else if(p_uart->tx_ptr == NULL) {
774 //Update the TX item pointer, we will need this to return item to buffer.
775 p_uart->tx_ptr = (uint8_t*) p_uart->tx_head;
777 p_uart->tx_len_cur = size;
781 //Can not get data from ring buffer, return;
785 if (p_uart->tx_len_tot > 0 && p_uart->tx_ptr && p_uart->tx_len_cur > 0) {
786 //To fill the TX FIFO.
787 int send_len = p_uart->tx_len_cur > tx_fifo_rem ? tx_fifo_rem : p_uart->tx_len_cur;
788 // Set RS485 RTS pin before transmission if the half duplex mode is enabled
789 if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)) {
790 UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
791 uart_reg->conf0.sw_rts = 0;
792 uart_reg->int_ena.tx_done = 1;
793 UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
795 for (buf_idx = 0; buf_idx < send_len; buf_idx++) {
796 WRITE_PERI_REG(UART_FIFO_AHB_REG(uart_num),
797 *(p_uart->tx_ptr++) & 0xff);
799 p_uart->tx_len_tot -= send_len;
800 p_uart->tx_len_cur -= send_len;
801 tx_fifo_rem -= send_len;
802 if (p_uart->tx_len_cur == 0) {
803 //Return item to ring buffer.
804 vRingbufferReturnItemFromISR(p_uart->tx_ring_buf, p_uart->tx_head, &HPTaskAwoken);
805 if(HPTaskAwoken == pdTRUE) {
806 portYIELD_FROM_ISR();
808 p_uart->tx_head = NULL;
809 p_uart->tx_ptr = NULL;
810 //Sending item done, now we need to send break if there is a record.
811 //Set TX break signal after FIFO is empty
812 if(p_uart->tx_brk_flg == 1 && p_uart->tx_len_tot == 0) {
813 UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
814 uart_reg->int_ena.tx_brk_done = 0;
815 uart_reg->idle_conf.tx_brk_num = p_uart->tx_brk_len;
816 uart_reg->conf0.txd_brk = 1;
817 uart_reg->int_clr.tx_brk_done = 1;
818 uart_reg->int_ena.tx_brk_done = 1;
819 UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
820 p_uart->tx_waiting_brk = 1;
822 //enable TX empty interrupt
826 //enable TX empty interrupt
832 uart_clear_intr_status(uart_num, UART_TXFIFO_EMPTY_INT_CLR_M);
833 uart_enable_intr_mask(uart_num, UART_TXFIFO_EMPTY_INT_ENA_M);
837 else if ((uart_intr_status & UART_RXFIFO_TOUT_INT_ST_M)
838 || (uart_intr_status & UART_RXFIFO_FULL_INT_ST_M)
839 || (uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M)
841 rx_fifo_len = uart_reg->status.rxfifo_cnt;
843 uart_intr_status |= UART_AT_CMD_CHAR_DET_INT_ST_M;
846 if (p_uart->rx_buffer_full_flg == false) {
847 //We have to read out all data in RX FIFO to clear the interrupt signal
848 while (buf_idx < rx_fifo_len) {
849 p_uart->rx_data_buf[buf_idx++] = uart_reg->fifo.rw_byte;
851 uint8_t pat_chr = uart_reg->at_cmd_char.data;
852 int pat_num = uart_reg->at_cmd_char.char_num;
855 //Get the buffer from the FIFO
856 if (uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) {
857 uart_clear_intr_status(uart_num, UART_AT_CMD_CHAR_DET_INT_CLR_M);
858 uart_event.type = UART_PATTERN_DET;
859 uart_event.size = rx_fifo_len;
860 pat_idx = uart_find_pattern_from_last(p_uart->rx_data_buf, rx_fifo_len - 1, pat_chr, pat_num);
862 //After Copying the Data From FIFO ,Clear intr_status
863 uart_clear_intr_status(uart_num, UART_RXFIFO_TOUT_INT_CLR_M | UART_RXFIFO_FULL_INT_CLR_M);
864 uart_event.type = UART_DATA;
865 uart_event.size = rx_fifo_len;
866 UART_ENTER_CRITICAL_ISR(&uart_selectlock);
867 if (p_uart->uart_select_notif_callback) {
868 p_uart->uart_select_notif_callback(uart_num, UART_SELECT_READ_NOTIF, &HPTaskAwoken);
870 UART_EXIT_CRITICAL_ISR(&uart_selectlock);
872 p_uart->rx_stash_len = rx_fifo_len;
873 //If we fail to push data to ring buffer, we will have to stash the data, and send next time.
874 //Mainly for applications that uses flow control or small ring buffer.
875 if(pdFALSE == xRingbufferSendFromISR(p_uart->rx_ring_buf, p_uart->rx_data_buf, p_uart->rx_stash_len, &HPTaskAwoken)) {
876 uart_disable_intr_mask(uart_num, UART_RXFIFO_TOUT_INT_ENA_M | UART_RXFIFO_FULL_INT_ENA_M);
877 if (uart_event.type == UART_PATTERN_DET) {
878 if (rx_fifo_len < pat_num) {
879 //some of the characters are read out in last interrupt
880 uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len - (pat_num - rx_fifo_len));
882 uart_pattern_enqueue(uart_num,
884 //can not find the pattern in buffer,
885 p_uart->rx_buffered_len + p_uart->rx_stash_len :
886 // find the pattern in buffer
887 p_uart->rx_buffered_len + pat_idx);
889 if ((p_uart->xQueueUart != NULL) && (pdFALSE == xQueueSendFromISR(p_uart->xQueueUart, (void * )&uart_event, &HPTaskAwoken))) {
890 ESP_EARLY_LOGV(UART_TAG, "UART event queue full");
893 uart_event.type = UART_BUFFER_FULL;
894 p_uart->rx_buffer_full_flg = true;
896 UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
897 if (uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) {
898 if (rx_fifo_len < pat_num) {
899 //some of the characters are read out in last interrupt
900 uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len - (pat_num - rx_fifo_len));
901 } else if(pat_idx >= 0) {
902 // find pattern in statsh buffer.
903 uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len + pat_idx);
906 p_uart->rx_buffered_len += p_uart->rx_stash_len;
907 UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
909 if(HPTaskAwoken == pdTRUE) {
910 portYIELD_FROM_ISR();
913 uart_disable_intr_mask(uart_num, UART_RXFIFO_FULL_INT_ENA_M | UART_RXFIFO_TOUT_INT_ENA_M);
914 uart_clear_intr_status(uart_num, UART_RXFIFO_FULL_INT_CLR_M | UART_RXFIFO_TOUT_INT_CLR_M);
915 if(uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) {
916 uart_reg->int_clr.at_cmd_char_det = 1;
917 uart_event.type = UART_PATTERN_DET;
918 uart_event.size = rx_fifo_len;
922 } else if(uart_intr_status & UART_RXFIFO_OVF_INT_ST_M) {
923 // When fifo overflows, we reset the fifo.
924 UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
925 uart_reset_rx_fifo(uart_num);
926 uart_reg->int_clr.rxfifo_ovf = 1;
927 UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
928 uart_event.type = UART_FIFO_OVF;
929 UART_ENTER_CRITICAL_ISR(&uart_selectlock);
930 if (p_uart->uart_select_notif_callback) {
931 p_uart->uart_select_notif_callback(uart_num, UART_SELECT_ERROR_NOTIF, &HPTaskAwoken);
933 UART_EXIT_CRITICAL_ISR(&uart_selectlock);
934 } else if(uart_intr_status & UART_BRK_DET_INT_ST_M) {
935 uart_reg->int_clr.brk_det = 1;
936 uart_event.type = UART_BREAK;
937 } else if(uart_intr_status & UART_FRM_ERR_INT_ST_M) {
938 uart_reg->int_clr.frm_err = 1;
939 uart_event.type = UART_FRAME_ERR;
940 UART_ENTER_CRITICAL_ISR(&uart_selectlock);
941 if (p_uart->uart_select_notif_callback) {
942 p_uart->uart_select_notif_callback(uart_num, UART_SELECT_ERROR_NOTIF, &HPTaskAwoken);
944 UART_EXIT_CRITICAL_ISR(&uart_selectlock);
945 } else if(uart_intr_status & UART_PARITY_ERR_INT_ST_M) {
946 uart_reg->int_clr.parity_err = 1;
947 uart_event.type = UART_PARITY_ERR;
948 UART_ENTER_CRITICAL_ISR(&uart_selectlock);
949 if (p_uart->uart_select_notif_callback) {
950 p_uart->uart_select_notif_callback(uart_num, UART_SELECT_ERROR_NOTIF, &HPTaskAwoken);
952 UART_EXIT_CRITICAL_ISR(&uart_selectlock);
953 } else if(uart_intr_status & UART_TX_BRK_DONE_INT_ST_M) {
954 UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
955 uart_reg->conf0.txd_brk = 0;
956 uart_reg->int_ena.tx_brk_done = 0;
957 uart_reg->int_clr.tx_brk_done = 1;
958 if(p_uart->tx_brk_flg == 1) {
959 uart_reg->int_ena.txfifo_empty = 1;
961 UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
962 if(p_uart->tx_brk_flg == 1) {
963 p_uart->tx_brk_flg = 0;
964 p_uart->tx_waiting_brk = 0;
966 xSemaphoreGiveFromISR(p_uart->tx_brk_sem, &HPTaskAwoken);
967 if(HPTaskAwoken == pdTRUE) {
968 portYIELD_FROM_ISR();
971 } else if(uart_intr_status & UART_TX_BRK_IDLE_DONE_INT_ST_M) {
972 uart_disable_intr_mask(uart_num, UART_TX_BRK_IDLE_DONE_INT_ENA_M);
973 uart_clear_intr_status(uart_num, UART_TX_BRK_IDLE_DONE_INT_CLR_M);
974 } else if(uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) {
975 uart_reg->int_clr.at_cmd_char_det = 1;
976 uart_event.type = UART_PATTERN_DET;
977 } else if ((uart_intr_status & UART_RS485_CLASH_INT_ST_M)
978 || (uart_intr_status & UART_RS485_FRM_ERR_INT_ENA)
979 || (uart_intr_status & UART_RS485_PARITY_ERR_INT_ENA)) {
980 // RS485 collision or frame error interrupt triggered
981 uart_clear_intr_status(uart_num, UART_RS485_CLASH_INT_CLR_M);
982 UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
983 uart_reset_rx_fifo(uart_num);
984 // Set collision detection flag
985 p_uart_obj[uart_num]->coll_det_flg = true;
986 UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
987 uart_event.type = UART_EVENT_MAX;
988 } else if(uart_intr_status & UART_TX_DONE_INT_ST_M) {
989 uart_disable_intr_mask(uart_num, UART_TX_DONE_INT_ENA_M);
990 uart_clear_intr_status(uart_num, UART_TX_DONE_INT_CLR_M);
991 // If RS485 half duplex mode is enable then reset FIFO and
992 // reset RTS pin to start receiver driver
993 if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)) {
994 UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
995 uart_reset_rx_fifo(uart_num); // Allows to avoid hardware issue with the RXFIFO reset
996 uart_reg->conf0.sw_rts = 1;
997 UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
999 xSemaphoreGiveFromISR(p_uart_obj[uart_num]->tx_done_sem, &HPTaskAwoken);
1000 if (HPTaskAwoken == pdTRUE) {
1001 portYIELD_FROM_ISR();
1004 uart_reg->int_clr.val = uart_intr_status; /*simply clear all other intr status*/
1005 uart_event.type = UART_EVENT_MAX;
1008 if(uart_event.type != UART_EVENT_MAX && p_uart->xQueueUart) {
1009 if (pdFALSE == xQueueSendFromISR(p_uart->xQueueUart, (void * )&uart_event, &HPTaskAwoken)) {
1010 ESP_EARLY_LOGV(UART_TAG, "UART event queue full");
1012 if(HPTaskAwoken == pdTRUE) {
1013 portYIELD_FROM_ISR();
1016 uart_intr_status = uart_reg->int_st.val;
1020 /**************************************************************/
1021 esp_err_t uart_wait_tx_done(uart_port_t uart_num, TickType_t ticks_to_wait)
1023 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
1024 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
1026 portTickType ticks_end = xTaskGetTickCount() + ticks_to_wait;
1028 res = xSemaphoreTake(p_uart_obj[uart_num]->tx_mux, (portTickType)ticks_to_wait);
1029 if(res == pdFALSE) {
1030 return ESP_ERR_TIMEOUT;
1032 ticks_to_wait = ticks_end - xTaskGetTickCount();
1033 xSemaphoreTake(p_uart_obj[uart_num]->tx_done_sem, 0);
1034 ticks_to_wait = ticks_end - xTaskGetTickCount();
1035 if(UART[uart_num]->status.txfifo_cnt == 0) {
1036 xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
1039 uart_enable_intr_mask(uart_num, UART_TX_DONE_INT_ENA_M);
1040 //take 2nd tx_done_sem, wait given from ISR
1041 res = xSemaphoreTake(p_uart_obj[uart_num]->tx_done_sem, (portTickType)ticks_to_wait);
1042 if(res == pdFALSE) {
1043 uart_disable_intr_mask(uart_num, UART_TX_DONE_INT_ENA_M);
1044 xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
1045 return ESP_ERR_TIMEOUT;
1047 xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
1051 static esp_err_t uart_set_break(uart_port_t uart_num, int break_num)
1053 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
1054 UART[uart_num]->idle_conf.tx_brk_num = break_num;
1055 UART[uart_num]->conf0.txd_brk = 1;
1056 UART[uart_num]->int_clr.tx_brk_done = 1;
1057 UART[uart_num]->int_ena.tx_brk_done = 1;
1058 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
1062 //Fill UART tx_fifo and return a number,
1063 //This function by itself is not thread-safe, always call from within a muxed section.
1064 static int uart_fill_fifo(uart_port_t uart_num, const char* buffer, uint32_t len)
1067 uint8_t tx_fifo_cnt = UART[uart_num]->status.txfifo_cnt;
1068 uint8_t tx_remain_fifo_cnt = (UART_FIFO_LEN - tx_fifo_cnt);
1069 uint8_t copy_cnt = (len >= tx_remain_fifo_cnt ? tx_remain_fifo_cnt : len);
1070 // Set the RTS pin if RS485 mode is enabled
1071 if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)) {
1072 UART[uart_num]->conf0.sw_rts = 0;
1073 UART[uart_num]->int_ena.tx_done = 1;
1075 for (i = 0; i < copy_cnt; i++) {
1076 WRITE_PERI_REG(UART_FIFO_AHB_REG(uart_num), buffer[i]);
1081 int uart_tx_chars(uart_port_t uart_num, const char* buffer, uint32_t len)
1083 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1));
1084 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
1085 UART_CHECK(buffer, "buffer null", (-1));
1089 xSemaphoreTake(p_uart_obj[uart_num]->tx_mux, (portTickType)portMAX_DELAY);
1090 int tx_len = uart_fill_fifo(uart_num, (const char*) buffer, len);
1091 xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
1095 static int uart_tx_all(uart_port_t uart_num, const char* src, size_t size, bool brk_en, int brk_len)
1100 size_t original_size = size;
1103 xSemaphoreTake(p_uart_obj[uart_num]->tx_mux, (portTickType)portMAX_DELAY);
1104 p_uart_obj[uart_num]->coll_det_flg = false;
1105 if(p_uart_obj[uart_num]->tx_buf_size > 0) {
1106 int max_size = xRingbufferGetMaxItemSize(p_uart_obj[uart_num]->tx_ring_buf);
1109 evt.tx_data.size = size;
1110 evt.tx_data.brk_len = brk_len;
1112 evt.type = UART_DATA_BREAK;
1114 evt.type = UART_DATA;
1116 xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void*) &evt, sizeof(uart_tx_data_t), portMAX_DELAY);
1118 int send_size = size > max_size / 2 ? max_size / 2 : size;
1119 xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void*) (src + offset), send_size, portMAX_DELAY);
1121 offset += send_size;
1122 uart_enable_tx_intr(uart_num, 1, UART_EMPTY_THRESH_DEFAULT);
1126 //semaphore for tx_fifo available
1127 if(pdTRUE == xSemaphoreTake(p_uart_obj[uart_num]->tx_fifo_sem, (portTickType)portMAX_DELAY)) {
1128 size_t sent = uart_fill_fifo(uart_num, (char*) src, size);
1130 p_uart_obj[uart_num]->tx_waiting_fifo = true;
1131 uart_enable_tx_intr(uart_num, 1, UART_EMPTY_THRESH_DEFAULT);
1138 uart_set_break(uart_num, brk_len);
1139 xSemaphoreTake(p_uart_obj[uart_num]->tx_brk_sem, (portTickType)portMAX_DELAY);
1141 xSemaphoreGive(p_uart_obj[uart_num]->tx_fifo_sem);
1143 xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
1144 return original_size;
1147 int uart_write_bytes(uart_port_t uart_num, const char* src, size_t size)
1149 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1));
1150 UART_CHECK((p_uart_obj[uart_num] != NULL), "uart driver error", (-1));
1151 UART_CHECK(src, "buffer null", (-1));
1152 return uart_tx_all(uart_num, src, size, 0, 0);
1155 int uart_write_bytes_with_break(uart_port_t uart_num, const char* src, size_t size, int brk_len)
1157 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1));
1158 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
1159 UART_CHECK((size > 0), "uart size error", (-1));
1160 UART_CHECK((src), "uart data null", (-1));
1161 UART_CHECK((brk_len > 0 && brk_len < 256), "break_num error", (-1));
1162 return uart_tx_all(uart_num, src, size, 1, brk_len);
1165 int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickType_t ticks_to_wait)
1167 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1));
1168 UART_CHECK((buf), "uart data null", (-1));
1169 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
1170 uint8_t* data = NULL;
1172 size_t copy_len = 0;
1174 if(xSemaphoreTake(p_uart_obj[uart_num]->rx_mux,(portTickType)ticks_to_wait) != pdTRUE) {
1178 if(p_uart_obj[uart_num]->rx_cur_remain == 0) {
1179 data = (uint8_t*) xRingbufferReceive(p_uart_obj[uart_num]->rx_ring_buf, &size, (portTickType) ticks_to_wait);
1181 p_uart_obj[uart_num]->rx_head_ptr = data;
1182 p_uart_obj[uart_num]->rx_ptr = data;
1183 p_uart_obj[uart_num]->rx_cur_remain = size;
1185 xSemaphoreGive(p_uart_obj[uart_num]->rx_mux);
1189 if(p_uart_obj[uart_num]->rx_cur_remain > length) {
1192 len_tmp = p_uart_obj[uart_num]->rx_cur_remain;
1194 memcpy(buf + copy_len, p_uart_obj[uart_num]->rx_ptr, len_tmp);
1195 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
1196 p_uart_obj[uart_num]->rx_buffered_len -= len_tmp;
1197 uart_pattern_queue_update(uart_num, len_tmp);
1198 p_uart_obj[uart_num]->rx_ptr += len_tmp;
1199 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
1200 p_uart_obj[uart_num]->rx_cur_remain -= len_tmp;
1201 copy_len += len_tmp;
1203 if(p_uart_obj[uart_num]->rx_cur_remain == 0) {
1204 vRingbufferReturnItem(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_head_ptr);
1205 p_uart_obj[uart_num]->rx_head_ptr = NULL;
1206 p_uart_obj[uart_num]->rx_ptr = NULL;
1207 if(p_uart_obj[uart_num]->rx_buffer_full_flg) {
1208 BaseType_t res = xRingbufferSend(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_data_buf, p_uart_obj[uart_num]->rx_stash_len, 1);
1210 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
1211 p_uart_obj[uart_num]->rx_buffered_len += p_uart_obj[uart_num]->rx_stash_len;
1212 p_uart_obj[uart_num]->rx_buffer_full_flg = false;
1213 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
1214 uart_enable_rx_intr(p_uart_obj[uart_num]->uart_num);
1220 xSemaphoreGive(p_uart_obj[uart_num]->rx_mux);
1224 esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t* size)
1226 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
1227 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
1228 *size = p_uart_obj[uart_num]->rx_buffered_len;
1232 esp_err_t uart_flush(uart_port_t uart_num) __attribute__((alias("uart_flush_input")));
1234 esp_err_t uart_flush_input(uart_port_t uart_num)
1236 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
1237 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
1238 uart_obj_t* p_uart = p_uart_obj[uart_num];
1242 //rx sem protect the ring buffer read related functions
1243 xSemaphoreTake(p_uart->rx_mux, (portTickType)portMAX_DELAY);
1244 uart_disable_rx_intr(p_uart_obj[uart_num]->uart_num);
1246 if(p_uart->rx_head_ptr) {
1247 vRingbufferReturnItem(p_uart->rx_ring_buf, p_uart->rx_head_ptr);
1248 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
1249 p_uart_obj[uart_num]->rx_buffered_len -= p_uart->rx_cur_remain;
1250 uart_pattern_queue_update(uart_num, p_uart->rx_cur_remain);
1251 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
1252 p_uart->rx_ptr = NULL;
1253 p_uart->rx_cur_remain = 0;
1254 p_uart->rx_head_ptr = NULL;
1256 data = (uint8_t*) xRingbufferReceive(p_uart->rx_ring_buf, &size, (portTickType) 0);
1258 if( p_uart_obj[uart_num]->rx_buffered_len != 0 ) {
1259 ESP_LOGE(UART_TAG, "rx_buffered_len error");
1260 p_uart_obj[uart_num]->rx_buffered_len = 0;
1262 //We also need to clear the `rx_buffer_full_flg` here.
1263 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
1264 p_uart_obj[uart_num]->rx_buffer_full_flg = false;
1265 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
1268 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
1269 p_uart_obj[uart_num]->rx_buffered_len -= size;
1270 uart_pattern_queue_update(uart_num, size);
1271 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
1272 vRingbufferReturnItem(p_uart->rx_ring_buf, data);
1273 if(p_uart_obj[uart_num]->rx_buffer_full_flg) {
1274 BaseType_t res = xRingbufferSend(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_data_buf, p_uart_obj[uart_num]->rx_stash_len, 1);
1276 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
1277 p_uart_obj[uart_num]->rx_buffered_len += p_uart_obj[uart_num]->rx_stash_len;
1278 p_uart_obj[uart_num]->rx_buffer_full_flg = false;
1279 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
1283 p_uart->rx_ptr = NULL;
1284 p_uart->rx_cur_remain = 0;
1285 p_uart->rx_head_ptr = NULL;
1286 uart_reset_rx_fifo(uart_num);
1287 uart_enable_rx_intr(p_uart_obj[uart_num]->uart_num);
1288 xSemaphoreGive(p_uart->rx_mux);
1292 esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_buffer_size, int queue_size, QueueHandle_t *uart_queue, int intr_alloc_flags)
1295 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
1296 UART_CHECK((rx_buffer_size > UART_FIFO_LEN), "uart rx buffer length error(>128)", ESP_FAIL);
1297 UART_CHECK((tx_buffer_size > UART_FIFO_LEN) || (tx_buffer_size == 0), "uart tx buffer length error(>128 or 0)", ESP_FAIL);
1298 UART_CHECK((intr_alloc_flags & ESP_INTR_FLAG_IRAM) == 0, "ESP_INTR_FLAG_IRAM set in intr_alloc_flags", ESP_FAIL); /* uart_rx_intr_handler_default is not in IRAM */
1300 if(p_uart_obj[uart_num] == NULL) {
1301 p_uart_obj[uart_num] = (uart_obj_t*) calloc(1, sizeof(uart_obj_t));
1302 if(p_uart_obj[uart_num] == NULL) {
1303 ESP_LOGE(UART_TAG, "UART driver malloc error");
1306 p_uart_obj[uart_num]->uart_num = uart_num;
1307 p_uart_obj[uart_num]->uart_mode = UART_MODE_UART;
1308 p_uart_obj[uart_num]->coll_det_flg = false;
1309 p_uart_obj[uart_num]->tx_fifo_sem = xSemaphoreCreateBinary();
1310 xSemaphoreGive(p_uart_obj[uart_num]->tx_fifo_sem);
1311 p_uart_obj[uart_num]->tx_done_sem = xSemaphoreCreateBinary();
1312 p_uart_obj[uart_num]->tx_brk_sem = xSemaphoreCreateBinary();
1313 p_uart_obj[uart_num]->tx_mux = xSemaphoreCreateMutex();
1314 p_uart_obj[uart_num]->rx_mux = xSemaphoreCreateMutex();
1315 p_uart_obj[uart_num]->queue_size = queue_size;
1316 p_uart_obj[uart_num]->tx_ptr = NULL;
1317 p_uart_obj[uart_num]->tx_head = NULL;
1318 p_uart_obj[uart_num]->tx_len_tot = 0;
1319 p_uart_obj[uart_num]->tx_brk_flg = 0;
1320 p_uart_obj[uart_num]->tx_brk_len = 0;
1321 p_uart_obj[uart_num]->tx_waiting_brk = 0;
1322 p_uart_obj[uart_num]->rx_buffered_len = 0;
1323 uart_pattern_queue_reset(uart_num, UART_PATTERN_DET_QLEN_DEFAULT);
1326 p_uart_obj[uart_num]->xQueueUart = xQueueCreate(queue_size, sizeof(uart_event_t));
1327 *uart_queue = p_uart_obj[uart_num]->xQueueUart;
1328 ESP_LOGI(UART_TAG, "queue free spaces: %d", uxQueueSpacesAvailable(p_uart_obj[uart_num]->xQueueUart));
1330 p_uart_obj[uart_num]->xQueueUart = NULL;
1332 p_uart_obj[uart_num]->rx_buffer_full_flg = false;
1333 p_uart_obj[uart_num]->tx_waiting_fifo = false;
1334 p_uart_obj[uart_num]->rx_ptr = NULL;
1335 p_uart_obj[uart_num]->rx_cur_remain = 0;
1336 p_uart_obj[uart_num]->rx_head_ptr = NULL;
1337 p_uart_obj[uart_num]->rx_ring_buf = xRingbufferCreate(rx_buffer_size, RINGBUF_TYPE_BYTEBUF);
1338 if(tx_buffer_size > 0) {
1339 p_uart_obj[uart_num]->tx_ring_buf = xRingbufferCreate(tx_buffer_size, RINGBUF_TYPE_NOSPLIT);
1340 p_uart_obj[uart_num]->tx_buf_size = tx_buffer_size;
1342 p_uart_obj[uart_num]->tx_ring_buf = NULL;
1343 p_uart_obj[uart_num]->tx_buf_size = 0;
1345 p_uart_obj[uart_num]->uart_select_notif_callback = NULL;
1347 ESP_LOGE(UART_TAG, "UART driver already installed");
1351 r=uart_isr_register(uart_num, uart_rx_intr_handler_default, p_uart_obj[uart_num], intr_alloc_flags, &p_uart_obj[uart_num]->intr_handle);
1352 if (r!=ESP_OK) goto err;
1353 uart_intr_config_t uart_intr = {
1354 .intr_enable_mask = UART_RXFIFO_FULL_INT_ENA_M
1355 | UART_RXFIFO_TOUT_INT_ENA_M
1356 | UART_FRM_ERR_INT_ENA_M
1357 | UART_RXFIFO_OVF_INT_ENA_M
1358 | UART_BRK_DET_INT_ENA_M
1359 | UART_PARITY_ERR_INT_ENA_M,
1360 .rxfifo_full_thresh = UART_FULL_THRESH_DEFAULT,
1361 .rx_timeout_thresh = UART_TOUT_THRESH_DEFAULT,
1362 .txfifo_empty_intr_thresh = UART_EMPTY_THRESH_DEFAULT
1364 r=uart_intr_config(uart_num, &uart_intr);
1365 if (r!=ESP_OK) goto err;
1369 uart_driver_delete(uart_num);
1373 //Make sure no other tasks are still using UART before you call this function
1374 esp_err_t uart_driver_delete(uart_port_t uart_num)
1376 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
1377 if(p_uart_obj[uart_num] == NULL) {
1378 ESP_LOGI(UART_TAG, "ALREADY NULL");
1381 esp_intr_free(p_uart_obj[uart_num]->intr_handle);
1382 uart_disable_rx_intr(uart_num);
1383 uart_disable_tx_intr(uart_num);
1384 uart_pattern_link_free(uart_num);
1386 if(p_uart_obj[uart_num]->tx_fifo_sem) {
1387 vSemaphoreDelete(p_uart_obj[uart_num]->tx_fifo_sem);
1388 p_uart_obj[uart_num]->tx_fifo_sem = NULL;
1390 if(p_uart_obj[uart_num]->tx_done_sem) {
1391 vSemaphoreDelete(p_uart_obj[uart_num]->tx_done_sem);
1392 p_uart_obj[uart_num]->tx_done_sem = NULL;
1394 if(p_uart_obj[uart_num]->tx_brk_sem) {
1395 vSemaphoreDelete(p_uart_obj[uart_num]->tx_brk_sem);
1396 p_uart_obj[uart_num]->tx_brk_sem = NULL;
1398 if(p_uart_obj[uart_num]->tx_mux) {
1399 vSemaphoreDelete(p_uart_obj[uart_num]->tx_mux);
1400 p_uart_obj[uart_num]->tx_mux = NULL;
1402 if(p_uart_obj[uart_num]->rx_mux) {
1403 vSemaphoreDelete(p_uart_obj[uart_num]->rx_mux);
1404 p_uart_obj[uart_num]->rx_mux = NULL;
1406 if(p_uart_obj[uart_num]->xQueueUart) {
1407 vQueueDelete(p_uart_obj[uart_num]->xQueueUart);
1408 p_uart_obj[uart_num]->xQueueUart = NULL;
1410 if(p_uart_obj[uart_num]->rx_ring_buf) {
1411 vRingbufferDelete(p_uart_obj[uart_num]->rx_ring_buf);
1412 p_uart_obj[uart_num]->rx_ring_buf = NULL;
1414 if(p_uart_obj[uart_num]->tx_ring_buf) {
1415 vRingbufferDelete(p_uart_obj[uart_num]->tx_ring_buf);
1416 p_uart_obj[uart_num]->tx_ring_buf = NULL;
1419 free(p_uart_obj[uart_num]);
1420 p_uart_obj[uart_num] = NULL;
1422 if (uart_num != CONFIG_CONSOLE_UART_NUM ) {
1423 if(uart_num == UART_NUM_0) {
1424 periph_module_disable(PERIPH_UART0_MODULE);
1425 } else if(uart_num == UART_NUM_1) {
1426 periph_module_disable(PERIPH_UART1_MODULE);
1427 } else if(uart_num == UART_NUM_2) {
1428 periph_module_disable(PERIPH_UART2_MODULE);
1434 void uart_set_select_notif_callback(uart_port_t uart_num, uart_select_notif_callback_t uart_select_notif_callback)
1436 if (uart_num < UART_NUM_MAX && p_uart_obj[uart_num]) {
1437 p_uart_obj[uart_num]->uart_select_notif_callback = (uart_select_notif_callback_t) uart_select_notif_callback;
1441 portMUX_TYPE *uart_get_selectlock()
1443 return &uart_selectlock;
1446 esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode)
1448 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_ERR_INVALID_STATE);
1449 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
1450 if ((mode == UART_MODE_RS485_COLLISION_DETECT) || (mode == UART_MODE_RS485_APP_CTRL)
1451 || (mode == UART_MODE_RS485_HALF_DUPLEX)) {
1452 UART_CHECK((UART[uart_num]->conf1.rx_flow_en != 1),
1453 "disable hw flowctrl before using RS485 mode", ESP_ERR_INVALID_ARG);
1455 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
1456 UART[uart_num]->rs485_conf.en = 0;
1457 UART[uart_num]->rs485_conf.tx_rx_en = 0;
1458 UART[uart_num]->rs485_conf.rx_busy_tx_en = 0;
1459 UART[uart_num]->conf0.irda_en = 0;
1460 UART[uart_num]->conf0.sw_rts = 0;
1462 case UART_MODE_UART:
1464 case UART_MODE_RS485_COLLISION_DETECT:
1465 // This mode allows read while transmitting that allows collision detection
1466 p_uart_obj[uart_num]->coll_det_flg = false;
1467 // Transmitter
\92s output signal loop back to the receiver
\92s input signal
1468 UART[uart_num]->rs485_conf.tx_rx_en = 0 ;
1469 // Transmitter should send data when its receiver is busy
1470 UART[uart_num]->rs485_conf.rx_busy_tx_en = 1;
1471 UART[uart_num]->rs485_conf.en = 1;
1472 // Enable collision detection interrupts
1473 uart_enable_intr_mask(uart_num, UART_RXFIFO_TOUT_INT_ENA
1474 | UART_RXFIFO_FULL_INT_ENA
1475 | UART_RS485_CLASH_INT_ENA
1476 | UART_RS485_FRM_ERR_INT_ENA
1477 | UART_RS485_PARITY_ERR_INT_ENA);
1479 case UART_MODE_RS485_APP_CTRL:
1480 // Application software control, remove echo
1481 UART[uart_num]->rs485_conf.rx_busy_tx_en = 1;
1482 UART[uart_num]->rs485_conf.en = 1;
1484 case UART_MODE_RS485_HALF_DUPLEX:
1485 // Enable receiver, sw_rts = 1 generates low level on RTS pin
1486 UART[uart_num]->conf0.sw_rts = 1;
1487 UART[uart_num]->rs485_conf.en = 1;
1488 // Must be set to 0 to automatically remove echo
1489 UART[uart_num]->rs485_conf.tx_rx_en = 0;
1490 // This is to void collision
1491 UART[uart_num]->rs485_conf.rx_busy_tx_en = 1;
1493 case UART_MODE_IRDA:
1494 UART[uart_num]->conf0.irda_en = 1;
1497 UART_CHECK(1, "unsupported uart mode", ESP_ERR_INVALID_ARG);
1500 p_uart_obj[uart_num]->uart_mode = mode;
1501 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
1505 esp_err_t uart_set_rx_timeout(uart_port_t uart_num, const uint8_t tout_thresh)
1507 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
1508 UART_CHECK((tout_thresh < 127), "tout_thresh max value is 126", ESP_ERR_INVALID_ARG);
1509 UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
1510 // The tout_thresh = 1, defines TOUT interrupt timeout equal to
1511 // transmission time of one symbol (~11 bit) on current baudrate
1512 if (tout_thresh > 0) {
1513 UART[uart_num]->conf1.rx_tout_thrhd = (tout_thresh & UART_RX_TOUT_THRHD_V);
1514 UART[uart_num]->conf1.rx_tout_en = 1;
1516 UART[uart_num]->conf1.rx_tout_en = 0;
1518 UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
1522 esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool* collision_flag)
1524 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
1525 UART_CHECK((collision_flag != NULL), "wrong parameter pointer", ESP_ERR_INVALID_ARG);
1526 UART_CHECK((UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)
1527 || UART_IS_MODE_SET(uart_num, UART_MODE_RS485_COLLISION_DETECT)),
1528 "wrong mode", ESP_ERR_INVALID_ARG);
1529 *collision_flag = p_uart_obj[uart_num]->coll_det_flg;