1 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
20 #include "freertos/FreeRTOS.h"
21 #include "freertos/queue.h"
24 /// Control tokens used to frame data transfers
25 /// (see section 7.3.3 of SD simplified spec)
27 /// Token sent before single/multi block reads and single block writes
28 #define TOKEN_BLOCK_START 0b11111110
29 /// Token sent before multi block writes
30 #define TOKEN_BLOCK_START_WRITE_MULTI 0b11111100
31 /// Token used to stop multi block write (for reads, CMD12 is used instead)
32 #define TOKEN_BLOCK_STOP_WRITE_MULTI 0b11111101
34 /// Data response tokens
36 /// Mask (high 3 bits are undefined for data response tokens)
37 #define TOKEN_RSP_MASK 0b11111
39 #define TOKEN_RSP_OK 0b00101
40 /// Data rejected due to CRC error
41 #define TOKEN_RSP_CRC_ERR 0b01011
42 /// Data rejected due to write error
43 #define TOKEN_RSP_WRITE_ERR 0b01101
46 /// Data error tokens have format 0b0000xyzw where xyzw are signle bit flags.
47 /// MASK and VAL are used to check if a token is an error token
48 #define TOKEN_ERR_MASK 0b11110000
49 #define TOKEN_ERR_VAL 0b00000000
51 /// Argument is out of range
52 #define TOKEN_ERR_RANGE BIT(3)
53 /// Card internal ECC error
54 #define TOKEN_ERR_CARD_ECC BIT(2)
55 /// Card controller error
56 #define TOKEN_ERR_INTERNAL BIT(1)
58 #define TOKEN_ERR_LOCKED BIT(0)
61 /// Transfer format in SPI mode. See section 7.3.1.1 of SD simplified spec.
63 // These fields form the command sent from host to the card (6 bytes)
64 uint8_t cmd_index : 6;
65 uint8_t transmission_bit : 1;
66 uint8_t start_bit : 1;
70 /// Ncr is the dead time between command and response; should be 0xff
72 /// Response data, should be set by host to 0xff for read operations
74 /// Up to 16 bytes of response. Luckily, this is aligned on 4 byte boundary.
76 /// response timeout, in milliseconds
80 #define SDSPI_CMD_NORESP_SIZE 6 //!< Size of the command without any response
81 #define SDSPI_CMD_R1_SIZE 8 //!< Size of the command with R1 response
82 #define SDSPI_CMD_R2_SIZE 9 //!< Size of the command with R1b response
83 #define SDSPI_CMD_R3_SIZE 12 //!< Size of the command with R3 response
84 #define SDSPI_CMD_R7_SIZE 12 //!< Size of the command with R7 response
86 #define SDSPI_CMD_FLAG_DATA BIT(0) //!< Command has data transfer
87 #define SDSPI_CMD_FLAG_WRITE BIT(1) //!< Data is written to the card
88 #define SDSPI_CMD_FLAG_RSP_R1 BIT(2) //!< Response format R1 (1 byte)
89 #define SDSPI_CMD_FLAG_RSP_R2 BIT(3) //!< Response format R2 (2 bytes)
90 #define SDSPI_CMD_FLAG_RSP_R3 BIT(4) //!< Response format R3 (5 bytes)
91 #define SDSPI_CMD_FLAG_RSP_R7 BIT(5) //!< Response format R7 (5 bytes)
92 #define SDSPI_CMD_FLAG_NORSP BIT(6) //!< Don't expect response (used when sending CMD0 first time).
94 #define SDSPI_MAX_DATA_LEN 512 //!< Max size of single block transfer
96 void make_hw_cmd(uint32_t opcode, uint32_t arg, int timeout_ms, sdspi_hw_cmd_t *hw_cmd);
98 esp_err_t sdspi_host_start_command(int slot, sdspi_hw_cmd_t *cmd,
99 void *data, uint32_t data_size, int flags);